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From:   Danila Tikhonov <danila@jiaxyga.com>
To:     agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Danila Tikhonov <danila@jiaxyga.com>,
        David Wronek <davidwronek@gmail.com>
Subject: [PATCH 1/2] dt-bindings: clock: Add SM7150 GCC clock binding
Date:   Mon,  9 Jan 2023 22:30:29 +0300
Message-Id: <20230109193030.42764-2-danila@jiaxyga.com>
In-Reply-To: <20230109193030.42764-1-danila@jiaxyga.com>
References: <20230109193030.42764-1-danila@jiaxyga.com>
MIME-Version: 1.0
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Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SM7150 SoCs.

Co-developed-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: David Wronek <davidwronek@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 .../bindings/clock/qcom,sm7150-gcc.yaml       |  50 +++++
 include/dt-bindings/clock/qcom,sm7150-gcc.h   | 193 ++++++++++++++++++
 2 files changed, 243 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,sm7150-gcc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
new file mode 100644
index 000000000000..6ce7a1877b00
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on SM7150
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on SM7150
+
+  See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h
+
+properties:
+  compatible:
+    const: qcom,sm7150-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board XO Active-Only source
+      - description: Sleep clock source
+
+required:
+  - compatible
+  - clocks
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,sm7150-gcc";
+      reg = <0x00100000 0x001f0000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
\ No newline at end of file
diff --git a/include/dt-bindings/clock/qcom,sm7150-gcc.h b/include/dt-bindings/clock/qcom,sm7150-gcc.h
new file mode 100644
index 000000000000..3e5f8d32796d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm7150-gcc.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com>
+ * Copyright (c) 2023, David Wronek <davidwronek@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
+
+/* GCC clock registers */
+#define GCC_GPLL0_MAIN_DIV_CDIV				0
+#define GPLL0						1
+#define GPLL0_OUT_EVEN					2
+#define GPLL6						3
+#define GPLL7						4
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK			5
+#define GCC_AGGRE_UFS_PHY_AXI_CLK			6
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK		7
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK			8
+#define GCC_APC_VS_CLK					9
+#define GCC_BOOT_ROM_AHB_CLK				10
+#define GCC_CAMERA_AHB_CLK				11
+#define GCC_CAMERA_HF_AXI_CLK				12
+#define GCC_CAMERA_SF_AXI_CLK				13
+#define GCC_CAMERA_XO_CLK				14
+#define GCC_CE1_AHB_CLK					15
+#define GCC_CE1_AXI_CLK					16
+#define GCC_CE1_CLK					17
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK			18
+#define GCC_CPUSS_AHB_CLK				19
+#define GCC_CPUSS_AHB_CLK_SRC				20
+#define GCC_CPUSS_GNOC_CLK				21
+#define GCC_CPUSS_RBCPR_CLK				22
+#define GCC_CPUSS_RBCPR_CLK_SRC				23
+#define GCC_DDRSS_GPU_AXI_CLK				24
+#define GCC_DISP_AHB_CLK				25
+#define GCC_DISP_GPLL0_CLK_SRC				26
+#define GCC_DISP_GPLL0_DIV_CLK_SRC			27
+#define GCC_DISP_HF_AXI_CLK				28
+#define GCC_DISP_SF_AXI_CLK				29
+#define GCC_DISP_XO_CLK					30
+#define GCC_GP1_CLK					31
+#define GCC_GP1_CLK_SRC					32
+#define GCC_GP2_CLK					33
+#define GCC_GP2_CLK_SRC					34
+#define GCC_GP3_CLK					35
+#define GCC_GP3_CLK_SRC					36
+#define GCC_GPU_CFG_AHB_CLK				37
+#define GCC_GPU_GPLL0_CLK_SRC				38
+#define GCC_GPU_GPLL0_DIV_CLK_SRC			39
+#define GCC_GPU_MEMNOC_GFX_CLK				40
+#define GCC_GPU_SNOC_DVM_GFX_CLK			41
+#define GCC_GPU_VS_CLK					42
+#define GCC_NPU_AXI_CLK					43
+#define GCC_NPU_CFG_AHB_CLK				44
+#define GCC_NPU_GPLL0_CLK_SRC				45
+#define GCC_NPU_GPLL0_DIV_CLK_SRC			46
+#define GCC_PCIE_0_AUX_CLK				47
+#define GCC_PCIE_0_AUX_CLK_SRC				48
+#define GCC_PCIE_0_CFG_AHB_CLK				49
+#define GCC_PCIE_0_CLKREF_CLK				50
+#define GCC_PCIE_0_MSTR_AXI_CLK				51
+#define GCC_PCIE_0_PIPE_CLK				52
+#define GCC_PCIE_0_SLV_AXI_CLK				53
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK			54
+#define GCC_PCIE_PHY_AUX_CLK				55
+#define GCC_PCIE_PHY_REFGEN_CLK				56
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC			57
+#define GCC_PDM2_CLK					58
+#define GCC_PDM2_CLK_SRC				59
+#define GCC_PDM_AHB_CLK					60
+#define GCC_PDM_XO4_CLK					61
+#define GCC_PRNG_AHB_CLK				62
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK			63
+#define GCC_QUPV3_WRAP0_CORE_CLK			64
+#define GCC_QUPV3_WRAP0_S0_CLK				65
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC			66
+#define GCC_QUPV3_WRAP0_S1_CLK				67
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC			68
+#define GCC_QUPV3_WRAP0_S2_CLK				69
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC			70
+#define GCC_QUPV3_WRAP0_S3_CLK				71
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC			72
+#define GCC_QUPV3_WRAP0_S4_CLK				73
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC			74
+#define GCC_QUPV3_WRAP0_S5_CLK				75
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC			76
+#define GCC_QUPV3_WRAP0_S6_CLK				77
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC			78
+#define GCC_QUPV3_WRAP0_S7_CLK				79
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC			80
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK			81
+#define GCC_QUPV3_WRAP1_CORE_CLK			82
+#define GCC_QUPV3_WRAP1_S0_CLK				83
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC			84
+#define GCC_QUPV3_WRAP1_S1_CLK				85
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC			86
+#define GCC_QUPV3_WRAP1_S2_CLK				87
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC			88
+#define GCC_QUPV3_WRAP1_S3_CLK				89
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC			90
+#define GCC_QUPV3_WRAP1_S4_CLK				91
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC			92
+#define GCC_QUPV3_WRAP1_S5_CLK				93
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC			94
+#define GCC_QUPV3_WRAP1_S6_CLK				95
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC			96
+#define GCC_QUPV3_WRAP1_S7_CLK				97
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC			98
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK			99
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK			100
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK			101
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK			102
+#define GCC_SDCC1_AHB_CLK				103
+#define GCC_SDCC1_APPS_CLK				104
+#define GCC_SDCC1_APPS_CLK_SRC				105
+#define GCC_SDCC1_ICE_CORE_CLK				106
+#define GCC_SDCC1_ICE_CORE_CLK_SRC			107
+#define GCC_SDCC2_AHB_CLK				108
+#define GCC_SDCC2_APPS_CLK				109
+#define GCC_SDCC2_APPS_CLK_SRC				110
+#define GCC_SDCC4_AHB_CLK				111
+#define GCC_SDCC4_APPS_CLK				112
+#define GCC_SDCC4_APPS_CLK_SRC				113
+#define GCC_SYS_NOC_CPUSS_AHB_CLK			114
+#define GCC_TSIF_AHB_CLK				115
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK			116
+#define GCC_TSIF_REF_CLK				117
+#define GCC_TSIF_REF_CLK_SRC				118
+#define GCC_UFS_MEM_CLKREF_CLK				119
+#define GCC_UFS_PHY_AHB_CLK				120
+#define GCC_UFS_PHY_AXI_CLK				121
+#define GCC_UFS_PHY_AXI_CLK_SRC				122
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK			123
+#define GCC_UFS_PHY_ICE_CORE_CLK			124
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC			125
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK			126
+#define GCC_UFS_PHY_PHY_AUX_CLK				127
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC			128
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK			129
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK			130
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK			131
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK			132
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC			133
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK		134
+#define GCC_USB30_PRIM_MASTER_CLK			135
+#define GCC_USB30_PRIM_MASTER_CLK_SRC			136
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK			137
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC		138
+#define GCC_USB30_PRIM_SLEEP_CLK			139
+#define GCC_USB3_PRIM_CLKREF_CLK			140
+#define GCC_USB3_PRIM_PHY_AUX_CLK			141
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC			142
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK			143
+#define GCC_USB3_PRIM_PHY_PIPE_CLK			144
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK			145
+#define GCC_VDDA_VS_CLK					146
+#define GCC_VDDCX_VS_CLK				147
+#define GCC_VDDMX_VS_CLK				148
+#define GCC_VIDEO_AHB_CLK				149
+#define GCC_VIDEO_AXI_CLK				150
+#define GCC_VIDEO_XO_CLK				151
+#define GCC_VS_CTRL_AHB_CLK				152
+#define GCC_VS_CTRL_CLK					153
+#define GCC_VS_CTRL_CLK_SRC				154
+#define GCC_VSENSOR_CLK_SRC				155
+
+/* GCC Resets */
+#define GCC_PCIE_0_BCR					0
+#define GCC_PCIE_PHY_BCR				1
+#define GCC_PCIE_PHY_COM_BCR				2
+#define GCC_UFS_PHY_BCR					3
+#define GCC_USB30_PRIM_BCR				4
+#define GCC_USB3_DP_PHY_PRIM_BCR			5
+#define GCC_USB3_DP_PHY_SEC_BCR				6
+#define GCC_USB3_PHY_PRIM_BCR				7
+#define GCC_USB3_PHY_SEC_BCR				8
+#define GCC_QUSB2PHY_PRIM_BCR				9
+#define GCC_VIDEO_AXI_CLK_BCR				10
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC					0
+#define UFS_PHY_GDSC					1
+#define USB30_PRIM_GDSC					2
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC		3
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC		4
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC		5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC		6
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC		7
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC		8
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC		9
+
+#endif
-- 
2.39.0