Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Willy Tarreau <w@1wt.eu>
To:     "Paul E. McKenney" <paulmck@kernel.org>
Cc:     linux-kernel@vger.kernel.org, Willy Tarreau <w@1wt.eu>
Subject: [PATCH v2 02/22] tools/nolibc: enable support for thumb1 mode for ARM
Date:   Tue, 10 Jan 2023 08:24:14 +0100
Message-Id: <20230110072434.3863-3-w@1wt.eu>
In-Reply-To: <20230110072434.3863-1-w@1wt.eu>
References: <20230110072434.3863-1-w@1wt.eu>
Precedence: bulk

Passing -mthumb to the kernel.org arm toolchain failed to build because it
defaults to armv5 hence thumb1, which has a fairly limited instruction set
compared to thumb2 enabled with armv7 that is much more complete. It's not
very difficult to adjust the instructions to also build on thumb1, it only
adds a total of 3 instructions, so it's worth doing it at least to ease use
by casual testers. It was verified that the adjusted code now builds and
works fine for armv5, thumb1, armv7 and thumb2, as long as frame pointers
are not used.

Signed-off-by: Willy Tarreau <w@1wt.eu>
---
 tools/include/nolibc/arch-arm.h | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tools/include/nolibc/arch-arm.h b/tools/include/nolibc/arch-arm.h
index 875b21975137..e4ba77b0310f 100644
--- a/tools/include/nolibc/arch-arm.h
+++ b/tools/include/nolibc/arch-arm.h
@@ -180,10 +180,16 @@ void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(void)
 	__asm__ volatile (
 		"pop {%r0}\n"                 // argc was in the stack
 		"mov %r1, %sp\n"              // argv = sp
-		"add %r2, %r1, %r0, lsl #2\n" // envp = argv + 4*argc ...
-		"add %r2, %r2, $4\n"          //        ... + 4
-		"and %r3, %r1, $-8\n"         // AAPCS : sp must be 8-byte aligned in the
-		"mov %sp, %r3\n"              //         callee, an bl doesn't push (lr=pc)
+
+		"add %r2, %r0, $1\n"          // envp = (argc + 1) ...
+		"lsl %r2, %r2, $2\n"          //        * 4        ...
+		"add %r2, %r2, %r1\n"         //        + argv
+
+		"mov %r3, $8\n"               // AAPCS : sp must be 8-byte aligned in the
+		"neg %r3, %r3\n"              //         callee, and bl doesn't push (lr=pc)
+		"and %r3, %r3, %r1\n"         // so we do sp = r1(=sp) & r3(=-8);
+		"mov %sp, %r3\n"              //
+
 		"bl main\n"                   // main() returns the status code, we'll exit with it.
 		"movs r7, $1\n"               // NR_exit == 1
 		"svc $0x00\n"
-- 
2.17.5