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Date:   Tue, 10 Jan 2023 15:20:53 +0300
From:   Serge Semin <fancer.lancer@gmail.com>
To:     Sudip Mukherjee <sudip.mukherjee@sifive.com>
Cc:     Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        jude.onyenegecha@sifive.com, ben.dooks@sifive.com,
        jeegar.lakhani@sifive.com, linux-spi@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 13/15] spi: dw: detect enhanced spi mode
Message-ID: <20230110122053.a4x2oyb5fbjoenia@mobilestation>
References: <20221212180732.79167-1-sudip.mukherjee@sifive.com>
 <20221212180732.79167-14-sudip.mukherjee@sifive.com>
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In-Reply-To: <20221212180732.79167-14-sudip.mukherjee@sifive.com>
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On Mon, Dec 12, 2022 at 06:07:30PM +0000, Sudip Mukherjee wrote:
> All the SSI controllers supporting enhanced spi modes might not support
> all the three dual or quad or octal modes. Detect the modes that are
> supported and finally enable the DW_SPI_CAP_EMODE capability which will
> start using all the enhanced spi functions that has been added.
> 
> Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
> ---
>  drivers/spi/spi-dw-core.c | 68 +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 66 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index cef56acd8d8fd..9e806d5878beb 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
> @@ -1143,6 +1143,69 @@ static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)
>  		dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
>  }
>  
> +static u16 detect_enh_mode(struct dw_spi *dws)
> +{

> +	u16 mode = 0;
> +	u32 tmp_spi_ctrlr0, tmp_ctrlr0, tmpdual, tmpquad, tmpoct;
> +
> +	if (dw_spi_ver_is_ge(dws, HSSI, 103A)) {
> +		tmpdual = FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK,
> +				     DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI);
> +		tmpquad = FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK,
> +				     DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI);
> +		tmpoct = FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK,
> +				    DW_SPI_CTRLR0_SPI_FRF_OCT_SPI);
> +	} else if (dw_spi_ver_is_ge(dws, PSSI, 400A)) {
> +		tmpdual = FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK,
> +				     DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI);
> +		tmpquad = FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK,
> +				     DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI);
> +		tmpoct = FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK,
> +				    DW_SPI_CTRLR0_SPI_FRF_OCT_SPI);

Seems too complicated. What about calculating the IP-core specific
offset and mask here and use them afterwards to create the test CTRLR0
CSR data?

> +	} else {
> +		return DW_SPI_CTRLR0_SPI_FRF_STD_SPI;
> +	}
> +
> +	tmp_ctrlr0 = dw_readl(dws, DW_SPI_CTRLR0);
> +	tmp_spi_ctrlr0 = dw_readl(dws, DW_SPI_SPI_CTRLR0);
> +	dw_spi_enable_chip(dws, 0);
> +

> +	/* test clock stretching */
> +	dw_writel(dws, DW_SPI_SPI_CTRLR0, DW_SPI_SPI_CTRLR0_CLK_STRETCH_EN);
> +	if ((DW_SPI_SPI_CTRLR0_CLK_STRETCH_EN & dw_readl(dws, DW_SPI_SPI_CTRLR0)) !=
> +	    DW_SPI_SPI_CTRLR0_CLK_STRETCH_EN)
> +		/*
> +		 * If clock stretching is not enabled then do not use
> +		 * enhanced mode.
> +		 */
> +		goto disable_enh;
> +

Clock stretching is eSPI-specific feature. So it should be checked
after making sure that the eSPI is available.

> +	/* test dual mode */
> +	dw_writel(dws, DW_SPI_CTRLR0, tmpdual);
> +	if ((tmpdual & dw_readl(dws, DW_SPI_CTRLR0)) == tmpdual)
> +		mode |= SPI_TX_DUAL | SPI_RX_DUAL;
> +
> +	/* test quad mode */
> +	dw_writel(dws, DW_SPI_CTRLR0, tmpquad);
> +	if ((tmpquad & dw_readl(dws, DW_SPI_CTRLR0)) == tmpquad)
> +		mode |= SPI_TX_QUAD | SPI_RX_QUAD;
> +
> +	/* test octal mode */
> +	dw_writel(dws, DW_SPI_CTRLR0, tmpoct);
> +	if ((tmpoct & dw_readl(dws, DW_SPI_CTRLR0)) == tmpoct)
> +		mode |= SPI_TX_OCTAL | SPI_RX_OCTAL;

Are you sure that writing a non-supported mode causes having the
CTRLR0.SPI_FRF field unupdated? What eSPI-modes do your hardware
support?

> +
> +	if (mode)
> +		dws->caps |= DW_SPI_CAP_EMODE;
> +
> +disable_enh:
> +	dw_writel(dws, DW_SPI_CTRLR0, tmp_ctrlr0);
> +	dw_writel(dws, DW_SPI_SPI_CTRLR0, tmp_spi_ctrlr0);
> +	dw_spi_enable_chip(dws, 1);
> +
> +	return mode;

Move all the above to the dw_spi_hw_init() method where all the
auto-detections is implemented.

-Serge(y)

> +}
> +
>  int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
>  {
>  	struct spi_controller *master;
> @@ -1172,10 +1235,11 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
>  		goto err_free_master;
>  	}
>  
> -	dw_spi_init_mem_ops(dws);
> -
>  	master->use_gpio_descriptors = true;
>  	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
> +	master->mode_bits |= detect_enh_mode(dws);
> +	dw_spi_init_mem_ops(dws);
> +
>  	if (dws->caps & DW_SPI_CAP_DFS32)
>  		master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
>  	else
> -- 
> 2.30.2
>