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Date:   Tue, 10 Jan 2023 16:13:18 -0800
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Subject: Re: [PATCH 1/7] x86/cpu: Enumerate LASS CPUID and CR4 bits
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To:     Sohil Mehta <sohil.mehta@intel.com>,
        Yian Chen <yian.chen@intel.com>, linux-kernel@vger.kernel.org,
        x86@kernel.org, Andy Lutomirski <luto@kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Ravi Shankar <ravi.v.shankar@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Paul Lai <paul.c.lai@intel.com>
References: <20230110055204.3227669-1-yian.chen@intel.com>
 <20230110055204.3227669-2-yian.chen@intel.com>
 <9d935618-8f84-2d6e-4f4c-9d38eec2ba67@intel.com>
From:   Dave Hansen <dave.hansen@intel.com>
In-Reply-To: <9d935618-8f84-2d6e-4f4c-9d38eec2ba67@intel.com>
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On 1/10/23 12:14, Sohil Mehta wrote:
> On 1/9/2023 9:51 PM, Yian Chen wrote:
>> LASS (Linear Address Space Separation) is a CPU feature to
>> prevent speculative address access in user/kernel mode.
> 
> Would it be better to say?
> 
> LASS (Linear Address Space Separation) is a security feature that
> intends to prevent unintentional speculative address access across
> user/kernel mode.

It's more than that, though.  The spec actually says this pretty nicely:

> Linear-address space separation (LASS) is an independent mechanism
> that enforces the same mode-based protections as paging but without
> traversing the paging structures. Because the protections enforced by
> LASS are applied before paging, “probes” by malicious software will
> provide no paging-based timing information

So, it's not _just_ that it can prevent some speculative accesses.  It
completely short-circuits paging itself and *ALL* of the baggage that
goes along with paging.

The TLB, mid-level caches, the page walker itself, the data cache
impact...  all of it.  Gone.

*THAT* is the important part here, IMNHO.