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Message-ID: <ab6a99da-e91b-20de-3126-3f1f94ce277b@linaro.org>
Date:   Wed, 11 Jan 2023 10:59:10 +0100
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Subject: Re: [PATCH] arm64: dts: qcom: sm8450: Add TCSR halt register space
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To:     Mukesh Ojha <quic_mojha@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org
Cc:     linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <1673428818-26112-1-git-send-email-quic_mojha@quicinc.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <1673428818-26112-1-git-send-email-quic_mojha@quicinc.com>
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On 11/01/2023 10:20, Mukesh Ojha wrote:
> Add TCSR register space and refer it from scm node, so that
> it can be used by SCM driver.
> 
> Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 5704750..e0fa733 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -270,6 +270,7 @@
>  	firmware {
>  		scm: scm {
>  			compatible = "qcom,scm-sm8450", "qcom,scm";
> +			qcom,dload-mode = <&tcsr 0x13000>;
>  			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
>  			#reset-cells = <1>;
>  		};
> @@ -1986,6 +1987,11 @@
>  			#hwlock-cells = <1>;
>  		};
>  
> +		tcsr: syscon@1fc0000 {
> +			compatible = "syscon";

This is not allowed by itself. You should have warnings when running
dtbs_check.

Best regards,
Krzysztof