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[83.9.2.45]) by smtp.gmail.com with ESMTPSA id d19-20020a196b13000000b004b550c26949sm2688197lfa.290.2023.01.11.04.04.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 04:04:10 -0800 (PST) Message-ID: <51a8bb85-8fda-2d79-f753-9461316bae9e@linaro.org> Date: Wed, 11 Jan 2023 13:04:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v6 4/6] arm64: dts: qcom: sm6125: Add UFS nodes Content-Language: en-US To: Lux Aliaga , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com Cc: ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, linux-hardening@vger.kernel.org, phone-devel@vger.kernel.org, martin.botka@somainline.org, marijn.suijten@somainline.org References: <20230108195336.388349-1-they@mint.lgbt> <20230108195336.388349-5-they@mint.lgbt> <475d3f2f-114f-d6d2-89db-465ba7acd0d6@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11.01.2023 03:53, Lux Aliaga wrote: > > On 09/01/2023 09:18, Konrad Dybcio wrote: >> >> On 8.01.2023 20:53, Lux Aliaga wrote: >>> Adds a UFS host controller node and its corresponding PHY to >>> the sm6125 platform. >>> >>> Signed-off-by: Lux Aliaga >>> --- >>>   arch/arm64/boot/dts/qcom/sm6125.dtsi | 57 ++++++++++++++++++++++++++++ >>>   1 file changed, 57 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>> index df5453fcf2b9..cec7071d5279 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>> @@ -511,6 +511,63 @@ sdhc_2: mmc@4784000 { >>>               status = "disabled"; >>>           }; >>>   +        ufs_mem_hc: ufs@4804000 { >>> +            compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >>> +            reg = <0x04804000 0x3000>, <0x04810000 0x8000>; >> You need reg-names for ICE to probe, otherwise the second reg sits unused. >> >>> +            interrupts = ; >>> +            phys = <&ufs_mem_phy>; >>> +            phy-names = "ufsphy"; >>> +            lanes-per-direction = <1>; >>> +            #reset-cells = <1>; >>> +            resets = <&gcc GCC_UFS_PHY_BCR>; >>> +            reset-names = "rst"; >>> +            iommus = <&apps_smmu 0x200 0x0>; >>> + >>> +            clock-names = "core_clk", >>> +                      "bus_aggr_clk", >>> +                      "iface_clk", >>> +                      "core_clk_unipro", >>> +                      "ref_clk", >>> +                      "tx_lane0_sync_clk", >>> +                      "rx_lane0_sync_clk", >>> +                      "ice_core_clk"; >>> +            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >>> +                 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, >>> +                 <&gcc GCC_UFS_PHY_AHB_CLK>, >>> +                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >>> +                 <&rpmcc RPM_SMD_XO_CLK_SRC>, >>> +                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >>> +                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >>> +                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >>> +            freq-table-hz = <50000000 240000000>, >>> +                    <0 0>, >>> +                    <0 0>, >>> +                    <37500000 150000000>, >>> +                    <0 0>, >>> +                    <0 0>, >>> +                    <0 0>, >>> +                    <75000000 300000000>; >>> + >>> +            status = "disabled"; >>> +        }; >>> + >>> +        ufs_mem_phy: phy@4807000 { >>> +            compatible = "qcom,sm6125-qmp-ufs-phy"; >>> +            reg = <0x04807000 0x1c4>; >> Isn't this too small? Downstream says 0xdb8, but it's probably even bigger.. > What do you think could help me find the new length of the registers? I tried 0x1000 and it probed just fine, but I'm not really sure until what extent I could push it. The "true" values are probably only in documentation, which I don't have. Konrad >