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Date:   Wed, 11 Jan 2023 16:14:19 -0600
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Jian Yang <jian.yang@mediatek.com>
Cc:     Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Jianjun Wang <jianjun.wang@mediatek.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Ryder Lee <ryder.lee@mediatek.com>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org,
        Project_Global_Chrome_Upstream_Group@mediatek.com,
        chuanjia.liu@mediatek.com, jieyy.yang@mediatek.com,
        qizhong.cheng@mediatek.com, rex-bc.chen@mediatek.com,
        david-yh.chiu@mediatek.com
Subject: Re: [PATCH 1/2] PCI: mediatek-gen3: Add power and reset control
 feature for downstream component
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In-Reply-To: <20230111032542.20306-2-jian.yang@mediatek.com>
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Hi,

On Wed, Jan 11, 2023 at 11:25:41AM +0800, Jian Yang wrote:
> From: "jian.yang" <jian.yang@mediatek.com>
> 
> Make MediaTek's controller driver capable of controlling power
> supplies and reset pin of a downstream component in power-on and
> power-off flow.
> 
> Some downstream components (e.g., a WIFI chip) may need an extra
> reset other than of PERST# and their power supplies, depending on
> the requirements of platform, may need to controlled by their
> parent's driver. To meet the requirements described above, I add this
> feature to MediaTek's PCIe controller driver as a optional feature.

Is this delay (dsc-reset-msleep) specific to a device downstream from
the MediaTek controller, not to the MediaTek controller itself?  If
so, it sounds like it should be a generic value that could be used by
other drivers, too.

How do you determine the value?  If there's some PCIe spec that
determines this, please include a citation to it.  

Bjorn