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Message-ID: <2b523ed5-a809-1354-1050-a4cc415a102c@intel.com>
Date:   Wed, 11 Jan 2023 14:22:23 -0800
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Subject: Re: [PATCH 5/7] x86/cpu: Enable LASS (Linear Address Space
 Separation)
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To:     Yian Chen <yian.chen@intel.com>, <linux-kernel@vger.kernel.org>,
        <x86@kernel.org>, Andy Lutomirski <luto@kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Ravi Shankar <ravi.v.shankar@intel.com>,
        "Tony Luck" <tony.luck@intel.com>, Paul Lai <paul.c.lai@intel.com>,
        Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
References: <20230110055204.3227669-1-yian.chen@intel.com>
 <20230110055204.3227669-6-yian.chen@intel.com>
From:   Sohil Mehta <sohil.mehta@intel.com>
In-Reply-To: <20230110055204.3227669-6-yian.chen@intel.com>
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> +static __always_inline void setup_lass(struct cpuinfo_x86 *c)
> +{
> +	if (cpu_feature_enabled(X86_FEATURE_LASS)) {
> +		cr4_set_bits(X86_CR4_LASS);
> +	} else {
> +		/*
> +		 * only clear the feature and cr4 bits when hardware
> +		 * supports LASS, in case it was enabled in a previous
> +		 * boot (e.g., via kexec)
> +		 */
> +		if (cpu_has(c, X86_FEATURE_LASS)) {
> +			cr4_clear_bits(X86_CR4_LASS);
> +			clear_cpu_cap(c, X86_FEATURE_LASS);
> +		}
> +	}
> +}

I am quite confused by the "else" code flow. Can you please help 
understand how this code path would be exercised?

Also, why don't other features such as SMAP or SMEP need this type of 
handling? I see something on similar lines for UMIP.

Also, how does the CR4 pinning code in the following patch play into 
this? Could it flag a warning when cr4_clear_bits() is called above?

> +
>   /* These bits should not change their value after CPU init is finished. */
>   static const unsigned long cr4_pinned_mask =
>   	X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
> @@ -1848,6 +1865,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
>   	setup_smep(c);
>   	setup_smap(c);
>   	setup_umip(c);
> +	setup_lass(c);
>