Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <880c4d3c-86d2-082c-bb58-8212adc67ff3@linux.intel.com>
Date:   Wed, 11 Jan 2023 15:27:51 -0800
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Firefox/102.0 Thunderbird/102.4.2
Subject: Re: [PATCH V1] PCI/AER: Configure ECRC only AER is native
Content-Language: en-US
To:     Bjorn Helgaas <helgaas@kernel.org>
Cc:     Vidya Sagar <vidyas@nvidia.com>, bhelgaas@google.com,
        ruscur@russell.cc, oohall@gmail.com, treding@nvidia.com,
        jonathanh@nvidia.com, mmaddireddy@nvidia.com, kthota@nvidia.com,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        vsethi@nvidia.com, linuxppc-dev@lists.ozlabs.org,
        sagar.tv@gmail.com
References: <20230111231033.GA1714672@bhelgaas>
From:   Sathyanarayanan Kuppuswamy 
        <sathyanarayanan.kuppuswamy@linux.intel.com>
In-Reply-To: <20230111231033.GA1714672@bhelgaas>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Precedence: bulk

Hi,

On 1/11/23 3:10 PM, Bjorn Helgaas wrote:
> On Wed, Jan 11, 2023 at 01:42:21PM -0800, Sathyanarayanan Kuppuswamy wrote:
>> On 1/11/23 12:31 PM, Vidya Sagar wrote:
>>> As the ECRC configuration bits are part of AER registers, configure
>>> ECRC only if AER is natively owned by the kernel.
>>
>> ecrc command line option takes "bios/on/off" as possible options. It
>> does not clarify whether "on/off" choices can only be used if AER is
>> owned by OS or it can override the ownership of ECRC configuration 
>> similar to pcie_ports=native option. Maybe that needs to be clarified.
> 
> Good point, what do you think of an update like this:
> 
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 6cfa6e3996cf..f7b40a439194 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -4296,7 +4296,9 @@
>  				specified, e.g., 12@pci:8086:9c22:103c:198f
>  				for 4096-byte alignment.
>  		ecrc=		Enable/disable PCIe ECRC (transaction layer
> -				end-to-end CRC checking).
> +				end-to-end CRC checking).  Only effective
> +				if OS has native AER control (either granted by
> +				ACPI _OSC or forced via "pcie_ports=native").
>  				bios: Use BIOS/firmware settings. This is the
>  				the default.
>  				off: Turn ECRC off

Looks fine. But do we even need "bios" option? Since it is the default
value, I am not sure why we need to list that as an option again. IMO
this could be removed.

> 
> I don't know whether the "ecrc=" parameter is really needed.  If we
> were adding it today, I would ask "why not enable ECRC wherever it is
> supported?"  If there are devices where it's broken, we could always
> add quirks to disable it on a case-by-case basis.

Checking the original patch which added it, it looks like the intention
is to give option to boost performance over integrity.

commit 43c16408842b0eeb367c23a6fa540ce69f99e347
Author: Andrew Patterson <andrew.patterson@hp.com>
Date:   Wed Apr 22 16:52:09 2009 -0600

    PCI: Add support for turning PCIe ECRC on or off
    
    Adds support for PCI Express transaction layer end-to-end CRC checking
    (ECRC).  This patch will enable/disable ECRC checking by setting/clearing
    the ECRC Check Enable and/or ECRC Generation Enable bits for devices that
    support ECRC.
    
    The ECRC setting is controlled by the "pci=ecrc=<policy>" command-line
    option. If this option is not set or is set to 'bios", the enable and
    generation bits are left in whatever state that firmware/BIOS set them to.
    The "off" setting turns them off, and the "on" option turns them on (if the
    device supports it).
    
    Turning ECRC on or off can be a data integrity versus performance
    tradeoff.  In theory, turning it on will catch more data errors, turning
    it off means possibly better performance since CRC does not need to be
    calculated by the PCIe hardware and packet sizes are reduced.


> 
> But I think the patch below is the right thing to do for now.  Vidya,

Agree.

> did you trip over an issue because of this, e.g., a conflict between
> firmware use of AER and Linux use of it?  If so, maybe we could
> mention a symptom on the commit log.  But my guess is you probably
> found this by inspection.
> 
> Bjorn
> 
>>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>>> ---
>>>  drivers/pci/pcie/aer.c | 3 +++
>>>  1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
>>> index e2d8a74f83c3..730b47bdcdef 100644
>>> --- a/drivers/pci/pcie/aer.c
>>> +++ b/drivers/pci/pcie/aer.c
>>> @@ -184,6 +184,9 @@ static int disable_ecrc_checking(struct pci_dev *dev)
>>>   */
>>>  void pcie_set_ecrc_checking(struct pci_dev *dev)
>>>  {
>>> +	if (!pcie_aer_is_native(dev))
>>> +		return;
>>> +
>>>  	switch (ecrc_policy) {
>>>  	case ECRC_POLICY_DEFAULT:
>>>  		return;
>>
>> -- 
>> Sathyanarayanan Kuppuswamy
>> Linux Kernel Developer

-- 
Sathyanarayanan Kuppuswamy
Linux Kernel Developer