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From:   Mubin Sayyed <mubin.sayyed@amd.com>
To:     <robh+dt@kernel.org>, <treding@nvidia.com>,
        <u.kleine-koenig@pengutronix.de>, <linux-pwm@vger.kernel.org>,
        <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
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        <michal.simek@amd.com>, <siva.durga.prasad.paladugu@amd.com>,
        <mubin10@gmail.com>, Mubin Sayyed <mubin.sayyed@amd.com>
Subject: [LINUX PATCH 2/3] dt-bindings: timer: Update device tree bindings for cadence TTC PWM
Date:   Thu, 12 Jan 2023 12:45:25 +0530
Message-ID: <20230112071526.3035949-3-mubin.sayyed@amd.com>
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Cadence TTC can act as PWM device, it is supported through
separate PWM framework based driver. Decision to configure
specific TTC device as PWM or clocksource/clockevent would
be done based on presence of "#pwm-cells" property.

Also, interrupt property is not required for TTC PWM driver.
Updated bindings to support TTC PWM configuration.

Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
---
 .../devicetree/bindings/timer/cdns,ttc.yaml   | 25 ++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml
index 7d821fd480f6..2855e92e02e3 100644
--- a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml
+++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml
@@ -32,12 +32,26 @@ properties:
     description: |
       Bit width of the timer, necessary if not 16.
 
+  "#pwm-cells":
+    description: |
+      Required to configure TTC as PWM device, supported cells are 0 to 3.
+    minimum: 0
+    maximum: 3
+
 required:
   - compatible
   - reg
-  - interrupts
   - clocks
 
+allOf:
+  - if:
+      not:
+        required:
+          - "#pwm-cells"
+    then:
+      required:
+        - interrupts
+
 additionalProperties: false
 
 examples:
@@ -50,3 +64,12 @@ examples:
         clocks = <&cpu_clk 3>;
         timer-width = <32>;
     };
+
+  - |
+    ttc1: ttc1@f8002000 {
+        compatible = "cdns,ttc";
+        reg = <0xF8002000 0x1000>;
+        clocks = <&cpu_clk 3>;
+        timer-width = <32>;
+        #pwm-cells = <3>;
+    };
-- 
2.25.1