Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Thu, 12 Jan 2023 06:12:30 -0800
From:   Piyush Malgujar <pmalgujar@marvell.com>
To:     Adrian Hunter <adrian.hunter@intel.com>
CC:     <linux-mmc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <ulf.hansson@linaro.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>,
        <yamada.masahiro@socionext.com>, <devicetree@vger.kernel.org>,
        <jannadurai@marvell.com>, <cchavva@marvell.com>
Subject: Re: [PATCH 2/5] drivers: mmc: sdhci-cadence: enable
 MMC_SDHCI_IO_ACCESSORS
Message-ID: <20230112141230.GB6335@Dell2s-9>
References: <20221219142418.27949-1-pmalgujar@marvell.com>
 <20221219142418.27949-3-pmalgujar@marvell.com>
 <35ea0a7a-3d63-26b7-4dc3-69f6ca41909a@intel.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <35ea0a7a-3d63-26b7-4dc3-69f6ca41909a@intel.com>
User-Agent: Mutt/1.9.4 (2018-02-28)
Precedence: bulk

Hi Adrian, 

Thank you for the review comments.

On Wed, Jan 11, 2023 at 10:23:43AM +0200, Adrian Hunter wrote:
> On 19/12/22 16:24, Piyush Malgujar wrote:
> > From: Jayanthi Annadurai <jannadurai@marvell.com>
> > 
> > Add support for CONFIG_MMC_SDHCI_IO_ACCESSORS for controller
> > specific register read and write APIs.
> > 
> > Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> > Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> > ---
> >  drivers/mmc/host/Kconfig         | 12 ++++++
> >  drivers/mmc/host/sdhci-cadence.c | 63 ++++++++++++++++++++++++++++++++
> >  2 files changed, 75 insertions(+)
> > 
> > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> > index 5e19a961c34d7b5664ab2fd43cfba82dc90913ac..b5b2ae0bb4625bdb9d17acdbb1887c9caa3a1f32 100644
> > --- a/drivers/mmc/host/Kconfig
> > +++ b/drivers/mmc/host/Kconfig
> > @@ -262,6 +262,18 @@ config MMC_SDHCI_CADENCE
> >  
> >  	  If unsure, say N.
> >  
> > +config MMC_SDHCI_CN10K
> > +	tristate "SDHCI Cadence support for Marvell CN10K platforms"
> > +	select MMC_SDHCI_CADENCE
> > +	select MMC_SDHCI_IO_ACCESSORS
> 
> Probably better to just add MMC_SDHCI_IO_ACCESSORS to 
> config MMC_SDHCI_CADENCE and drop MMC_SDHCI_CN10K
> 

This reason behind this was to not force SDHCI_IO_ACCESSORS upon cadence users as some may not
require it owing to how cadence ip is integrated to soc.

> > +	help
> > +	  This selects the SDHCI cadence driver and IO Accessors
> > +	  for Marvell CN10K platforms
> > +
> > +	  If you have Marvell CN10K platform, say Y or M here.
> > +
> > +	  If unsure, say N.
> > +
> >  config MMC_SDHCI_CNS3XXX
> >  	tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
> >  	depends on ARCH_CNS3XXX || COMPILE_TEST
> > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> > index 5332d19e489be936d6814feba4f0fc046f5e130e..6bf703f15bc5be7e3be4cb1144b78ec3585ec540 100644
> > --- a/drivers/mmc/host/sdhci-cadence.c
> > +++ b/drivers/mmc/host/sdhci-cadence.c
> > @@ -449,6 +449,61 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
> >  
> >  static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
> >  
> > +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> > +static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
> > +{
> > +	return readl(host->ioaddr + reg);
> > +}
> > +
> > +static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
> > +{
> > +	writel(val, host->ioaddr + reg);
> > +}
> > +
> > +static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
> > +{
> > +	u32 val, regoff;
> > +
> > +	regoff = reg & ~3;
> > +
> > +	val = readl(host->ioaddr + regoff);
> > +	if ((reg & 0x3) == 0)
> > +		return (val & 0xFFFF);
> > +	else
> > +		return ((val >> 16) & 0xFFFF);
> > +}
> > +
> > +static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
> > +{
> > +	writew(val, host->ioaddr + reg);
> > +}
> > +
> > +static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
> > +{
> > +	u32 val, regoff;
> > +
> > +	regoff = reg & ~3;
> > +
> > +	val = readl(host->ioaddr + regoff);
> > +	switch (reg & 3) {
> > +	case 0:
> > +		return (val & 0xFF);
> > +	case 1:
> > +		return ((val >> 8) & 0xFF);
> > +	case 2:
> > +		return ((val >> 16) & 0xFF);
> > +	case 3:
> > +		return ((val >> 24) & 0xFF);
> > +	}
> > +	return 0;
> > +}
> > +
> > +static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
> > +{
> > +	writeb(val, host->ioaddr + reg);
> > +}
> > +#endif
> > +
> >  static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
> >  {
> >  	u32 delay_element = phy->d.delay_element_org;
> > @@ -1576,6 +1631,14 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> >  };
> >  
> >  static const struct sdhci_ops sdhci_cdns_sd6_ops = {
> > +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> > +	.read_l = sdhci_cdns_sd6_readl,
> > +	.write_l = sdhci_cdns_sd6_writel,
> > +	.read_w = sdhci_cdns_sd6_readw,
> > +	.write_w = sdhci_cdns_sd6_writew,
> > +	.read_b = sdhci_cdns_sd6_readb,
> > +	.write_b = sdhci_cdns_sd6_writeb,
> > +#endif
> >  	.get_max_clock = sdhci_cdns_get_max_clock,
> >  	.set_clock = sdhci_cdns_sd6_set_clock,
> >  	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
> 

Rest of the comments will be taken care in v2.

Thanks,
Piyush