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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id w1-20020a19c501000000b004cf6c56fdb5sm110641lfe.232.2023.01.12.13.15.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 13:15:57 -0800 (PST) Message-ID: <8ecb84b5-93a5-691d-4a7d-5daed0e432e4@linaro.org> Date: Thu, 12 Jan 2023 23:15:57 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v6 2/2] clk: qcom: Add QDU1000 and QRU1000 GCC support Content-Language: en-GB To: Melody Olvera , Andy Gross , Bjorn Andersson , Michael Turquette , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230112204446.30236-1-quic_molvera@quicinc.com> <20230112204446.30236-3-quic_molvera@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <20230112204446.30236-3-quic_molvera@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/01/2023 22:44, Melody Olvera wrote: > From: Taniya Das > > Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs. > > Signed-off-by: Taniya Das > Signed-off-by: Melody Olvera > Reviewed-by: Dmitry Baryshkov > --- > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-qdu1000.c | 2653 ++++++++++++++++++++++++++++++++ > 3 files changed, 2662 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-qdu1000.c > [skipped the rest] > +}; > + > +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { > + .reg = 0x9d064, > + .shift = 0, > + .width = 2, > + .parent_map = gcc_parent_map_7, > + .clkr = { > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_0_pipe_clk_src", > + .parent_data = gcc_parent_data_7, > + .num_parents = ARRAY_SIZE(gcc_parent_data_7), > + .ops = &clk_regmap_mux_closest_ops, I think this should use clk_regmap_phy_mux_ops. > + }, > + }, > +}; > +-- With best wishes Dmitry