Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <3b2c162f-7ba2-5e84-2389-a8686c772467@linux.intel.com>
Date:   Fri, 13 Jan 2023 10:36:37 +0800
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101
 Thunderbird/102.6.1
Cc:     baolu.lu@linux.intel.com,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        Jason Gunthorpe <jgg@nvidia.com>,
        Vasant Hegde <vasant.hegde@amd.com>,
        "Zhu, Tony" <tony.zhu@intel.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "iommu@lists.linux.dev" <iommu@lists.linux.dev>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Matt Fagnani <matt.fagnani@bell.net>
Subject: Re: [PATCH v2 1/1] PCI: Add translated request only flag for
 pci_enable_pasid()
Content-Language: en-US
To:     "Tian, Kevin" <kevin.tian@intel.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        "Rodel, Jorg" <jroedel@suse.de>
References: <20230113014409.752405-1-baolu.lu@linux.intel.com>
 <BN9PR11MB52765287D7C66D9CF52F143E8CC29@BN9PR11MB5276.namprd11.prod.outlook.com>
From:   Baolu Lu <baolu.lu@linux.intel.com>
In-Reply-To: <BN9PR11MB52765287D7C66D9CF52F143E8CC29@BN9PR11MB5276.namprd11.prod.outlook.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk

On 2023/1/13 10:24, Tian, Kevin wrote:
>> From: Lu Baolu <baolu.lu@linux.intel.com>
>> Sent: Friday, January 13, 2023 9:44 AM
>>
>> One alternative is ATS which lets the device resolve the PASID+addr pair
>> before a memory request is made into a routeable TLB address through the
>> TA. Those resolved addresses are then cached on the device instead of
>> in the IOMMU TLB and the device always sets the translated bit for PASID.
>> One example of those devices are AMD graphic devices that always have ACS
>> or ATS enabled together with PASID.
> 
> this should be made clear that ATS alone doesn't imply that translated
> bit is always set. It's just an optimization so the device may cache
> translation for selective requests. Only combining with PRI to
> support SVA has such implication.
> 
>> + * @flags: device-specific flags
>> + *   - PCI_PASID_XLATED_REQ_ONLY: The PCI device only issues PASID
>> + *                                memory requests of translated type.
> 
> this reads like the device even doesn't issue non-PASID requests.
> 
> It is clearer to be "The PCI device always use translated type for all
> PASID memory requests".
> 
> Otherwise looks good to me:
> 
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>

Both make sense to me. It's updated. Thanks a lot!

--
Best regards,
baolu