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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2023 13:51:14.7289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a9bd4bc-63cb-43b6-ac0b-08daf56d3cf5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT113.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7894 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, NICE_REPLY_A,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/12/22 21:16, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 20.12.2022 19:02, Sumit Gupta пишет: >> Add support to use OPP table from DT in Tegra194 cpufreq driver. >> Tegra SoC's receive the frequency lookup table (LUT) from BPMP-FW. >> Cross check the OPP's present in DT against the LUT from BPMP-FW >> and enable only those DT OPP's which are present in LUT also. >> >> The OPP table in DT has CPU Frequency to bandwidth mapping where >> the bandwidth value is per MC channel. DRAM bandwidth depends on the >> number of MC channels which can vary as per the boot configuration. >> This per channel bandwidth from OPP table will be later converted by >> MC driver to final bandwidth value by multiplying with number of >> channels before sending the request to BPMP-FW. >> >> If OPP table is not present in DT, then use the LUT from BPMP-FW directy >> as the frequency table and not do the DRAM frequency scaling which is >> same as the current behavior. >> >> Now, as the CPU Frequency table is being controlling through OPP table >> in DT. Keeping fewer entries in the table will create less frequency >> steps and scale fast to high frequencies if required. > > It's not exactly clear what you're doing here. Are you going to scale > memory BW based on CPU freq? If yes, then this is wrong because CPU freq > is independent from the memory subsystem. > > All Tegra30+ SoCs have ACTMON hardware unit that monitors CPU memory > activity and CPU memory BW should be scaled based on CPU memory events > counter. We have ACTMON devfreq driver for older SoCs. I have no clue > how ACTMON can be accessed on T186+, perhaps there should be a BPMP FW > API for that. > Yes, scaling the memory BW based on CPU freq. Referred below patch set for previous generation of Tegra Soc's which you mentioned and tried to trace the history. https://patchwork.ozlabs.org/project/linux-tegra/patch/1418719298-25314-3-git-send-email-tomeu.vizoso@collabora.com/ In new Tegra Soc's, actmon counter control and usage has been moved to BPMP-FW where only 'MCALL' counter is used and 'MCCPU is not being used. Using the actmon counter was a reactive way to scale the frequency which is less effective due to averaging over a time period. We are now using the proactive way where clients tell their bandwidth needs to help achieve better performance.