Received: by 2002:a05:6358:a55:b0:ec:fcf4:3ecf with SMTP id 21csp972660rwb; Fri, 13 Jan 2023 06:28:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXudM25Xicr+3GpRU/zXpcBxMtC57kzJ0FtSWsJXoDjV/NYAI/dYFs7kkooQX/gI2uvg5v81 X-Received: by 2002:a05:6402:22ad:b0:488:6003:24b6 with SMTP id cx13-20020a05640222ad00b00488600324b6mr38932825edb.40.1673620112501; Fri, 13 Jan 2023 06:28:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673620112; cv=none; d=google.com; s=arc-20160816; b=Xg3/b6WRpR0Bq4Kb0RfyL9YreXV458wEdTdzMm6Vu7LSrQXF3hyUN4NkLOVlos4kzC hj1iFOudQDUZkBAo7fH2mUACSZq5ULBW/LOrW9Z5AxVYbPoxU84KaEw2KK0w1YSaSCs2 8ToPb1zhTfgbiai7cv5dA5pApSGaqDZFjIIftZKc/FolWPw6rTLdcZeFssiZuG5Icc5Y OloNx7DR8a9LAKuspbTz4q9LmAS4ukOHbgjqx0i2bXX+KTwQmnyZ7/Adg9fjLPaGPhtw NIy81GARc6gfP2chsuKiwRbRnrCJLwrX2GrFhEgL10YBL/f/SlnIQjx9N6fS2gvQluLi FAfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=HLMxgYnqS/4/TB7UwvI/vIGP7m316E2G7fHeJE1jpg8=; b=fyChRH5yphHc603NwHQqPErwDrxBWRfFwyhK5AttQjFBTF4g8Bo5vsYj52urfG9h6k g9TgOu8awYdTubMBC6mtcPfrs15nN3+6cGxw0QT7hHc3jn+NqUJdmhG65AO2NTAS+nLR 8+Cv/ZihKN33UqXZLsYMkh8QUPS7hUCireQNsVE4o57tLA7rGyprbJzFm8pgpBP4mhGW irnIKGETiR7TsXYe/AUSWDG7XXlWpIf2np6Gbwjf9mWovLtyB8vo672dvpK2DhrgD6rZ ZJxPjJUCSI20fJwBLCgTrkA6vSVjvjjq824oGcMj27WBWYxHX7Fuyukx0OidkWiCUrOs oD+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vanguardiasur-com-ar.20210112.gappssmtp.com header.s=20210112 header.b=AgTJXz4W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dt17-20020a170907729100b0084d1d7fbd27si22865571ejc.205.2023.01.13.06.28.19; Fri, 13 Jan 2023 06:28:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@vanguardiasur-com-ar.20210112.gappssmtp.com header.s=20210112 header.b=AgTJXz4W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241604AbjAMOQV (ORCPT + 53 others); Fri, 13 Jan 2023 09:16:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242112AbjAMOOC (ORCPT ); Fri, 13 Jan 2023 09:14:02 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E9576DBB2 for ; Fri, 13 Jan 2023 06:13:08 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id bu8so33282631lfb.4 for ; Fri, 13 Jan 2023 06:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HLMxgYnqS/4/TB7UwvI/vIGP7m316E2G7fHeJE1jpg8=; b=AgTJXz4WlI46LfMJr07WPO9BhmaVxpE2iOif1zm+Oqp2iZVRniRVH567A90yVL5zdT q1XZFC3xt7nD6cJNMVIvsOZecK0s9anCwlI3UWXh2ZdrPj0tZocJmc/VU9ZcuJg6dyTK APxb7T3i87E3Xsmq+DLDOIjYhftZV8wQrUz9GGXYm1vlT2HYb8Q8EXQCe5dVC28w94XB 5f7UeCZX30k7tILF7DrEO0D4HJzPbpfVs418KVMVGS9QCsqtum44qhS7GAzZ0+irSILU ipDxlxLSFw7DLoQehGVG7EYWuzAgSdyGCk1kY45FvWcJvcItZFLeF+D4HXs+ejyIVgO+ HwvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HLMxgYnqS/4/TB7UwvI/vIGP7m316E2G7fHeJE1jpg8=; b=fzVsZZNIxTVDwHvKq3jCqLw7CjLFNr3VD0TpPm06mxT5OxuFBWUVUFt9/tgpFqfnqX E2CBSez0g/C+uA1ayMct03hJe+cWNHsN+7bfN7c7WLH7lq//iVixH1KTYEV5X/+cnIWy ZvZtLwa+UT85SdNytnXVL3vJAnorv+UW4H+1gj6q4eQk/X9iWVJrXjaA4IxGxjVbX5TR 9xokmvy4lGYeGG59NXo//I7fTphOngbQgjmmU8A4qNPXOV754n2T+DAsgN82yPWlH7eL fYYa8t5iWjdFtsYqubxKJR4wHFRc19hBp1SAmxV53SKhgKO0ccxJtQq2jeOVAMhJYZ0r 5sTg== X-Gm-Message-State: AFqh2kofazAEZg7VNs/5xuqrAbQL8d/x44Co1CWCgRmx0AbVp75E+Zs0 htjCQAlXC/FzxTNFjxOAFq0traCksOSIFKnlTgGqvw== X-Received: by 2002:a05:6512:708:b0:4ca:fab6:91db with SMTP id b8-20020a056512070800b004cafab691dbmr3403772lfs.202.1673619186692; Fri, 13 Jan 2023 06:13:06 -0800 (PST) MIME-Version: 1.0 References: <20230113131257.661079-1-benjamin.gaignard@collabora.com> In-Reply-To: <20230113131257.661079-1-benjamin.gaignard@collabora.com> From: Ezequiel Garcia Date: Fri, 13 Jan 2023 11:12:53 -0300 Message-ID: Subject: Re: [PATCH v2] media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats To: Benjamin Gaignard Cc: p.zabel@pengutronix.de, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, hverkuil-cisco@xs4all.nl, nicolas.dufresne@collabora.co.uk, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Benjamin, On Fri, Jan 13, 2023 at 10:13 AM Benjamin Gaignard wrote: > > When decoding a 10bits bitstreams HEVC driver should only expose > 10bits pixel formats. > To fulfill this requirement it is needed to call hantro_reset_raw_fmt() > when bit depth change and to correctly set match_depth in pixel formats > enumeration. > > Fixes: dc39473d0340 ("media: hantro: imx8m: Enable 10bit decoding") > > Signed-off-by: Benjamin Gaignard > --- > version 2: > - Also remove struct hantro_ctx *ctx variable in hantro_try_ctrl() > > .../media/platform/verisilicon/hantro_drv.c | 40 +++++++++++++++---- > .../media/platform/verisilicon/hantro_v4l2.c | 2 +- > .../media/platform/verisilicon/hantro_v4l2.h | 1 + > .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 + > 4 files changed, 36 insertions(+), 9 deletions(-) > > diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c > index 8cb4a68c9119..e824e87618db 100644 > --- a/drivers/media/platform/verisilicon/hantro_drv.c > +++ b/drivers/media/platform/verisilicon/hantro_drv.c > @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > > static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > { > - struct hantro_ctx *ctx; > - > - ctx = container_of(ctrl->handler, > - struct hantro_ctx, ctrl_handler); > - This change is unrelated to this commit. > if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { > const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; > > @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) > /* Only 8-bit and 10-bit are supported */ > return -EINVAL; > - > - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; > } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { > const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; > > @@ -286,6 +279,32 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) > return 0; > } > > +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct hantro_ctx *ctx; > + > + ctx = container_of(ctrl->handler, > + struct hantro_ctx, ctrl_handler); > + > + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); > + > + switch (ctrl->id) { > + case V4L2_CID_STATELESS_HEVC_SPS: > + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; > + int bit_depth = sps->bit_depth_luma_minus8 + 8; > + > + if (ctx->bit_depth != bit_depth) { > + ctx->bit_depth = bit_depth; > + hantro_reset_raw_fmt(ctx); We need to propagate the EBUSY error from hantro_set_fmt_cap, to hantro_reset_raw_fmt, so this operation can fail if the capture queue has buffers allocated. Keep in mind, we have to make sure the hantro_ctx state remains unchanged when the operation fails. The entire hantro_v4l2.c format negotiation is done without this case in mind (controls can change the format enumeration), so this new case needs some refactoring. I also think we need v4l2-compliance tests for it. Thanks! Ezequiel > + } > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) > { > struct hantro_ctx *ctx; > @@ -328,6 +347,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { > .try_ctrl = hantro_try_ctrl, > }; > > +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { > + .s_ctrl = hantro_hevc_s_ctrl, > + .try_ctrl = hantro_try_ctrl, > +}; > + > static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { > .s_ctrl = hantro_jpeg_s_ctrl, > }; > @@ -470,7 +494,7 @@ static const struct hantro_ctrl controls[] = { > .codec = HANTRO_HEVC_DECODER, > .cfg = { > .id = V4L2_CID_STATELESS_HEVC_SPS, > - .ops = &hantro_ctrl_ops, > + .ops = &hantro_hevc_ctrl_ops, > }, > }, { > .codec = HANTRO_HEVC_DECODER, > diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c > index 2c7a805289e7..0025e049dd26 100644 > --- a/drivers/media/platform/verisilicon/hantro_v4l2.c > +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c > @@ -398,7 +398,7 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx) > hantro_set_fmt_out(ctx, fmt); > } > > -static void > +void > hantro_reset_raw_fmt(struct hantro_ctx *ctx) > { > const struct hantro_fmt *raw_vpu_fmt; > diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.h b/drivers/media/platform/verisilicon/hantro_v4l2.h > index 64f6f57e9d7a..f642560aed93 100644 > --- a/drivers/media/platform/verisilicon/hantro_v4l2.h > +++ b/drivers/media/platform/verisilicon/hantro_v4l2.h > @@ -21,6 +21,7 @@ > extern const struct v4l2_ioctl_ops hantro_ioctl_ops; > extern const struct vb2_ops hantro_queue_ops; > > +void hantro_reset_raw_fmt(struct hantro_ctx *ctx); > void hantro_reset_fmts(struct hantro_ctx *ctx); > int hantro_get_format_depth(u32 fourcc); > const struct hantro_fmt * > diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > index b390228fd3b4..f850d8bddef6 100644 > --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c > @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_NV12, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_P010, > .codec_mode = HANTRO_MODE_NONE, > + .match_depth = true, > .postprocessed = true, > .frmsize = { > .min_width = FMT_MIN_WIDTH, > -- > 2.34.1 >