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Subject: [PATCH 1/6] dt-bindings: clock: Add YAML schemas for QCOM A73 PLL
Date:   Fri, 13 Jan 2023 20:06:42 +0530
Message-ID: <20230113143647.14961-2-quic_devipriy@quicinc.com>
In-Reply-To: <20230113143647.14961-1-quic_devipriy@quicinc.com>
References: <20230113143647.14961-1-quic_devipriy@quicinc.com>
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Add schema for primary CPU PLL found on few Qualcomm platforms.

Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 .../bindings/clock/qcom,a73pll.yaml           | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,a73pll.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,a73pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a73pll.yaml
new file mode 100644
index 000000000000..a0e81094db8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,a73pll.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,a73pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm A73 PLL clock
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+
+description:
+  The A73 PLL on few Qualcomm platforms is the main CPU PLL used for
+  frequencies above 1GHz.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq9574-a73pll
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+  clocks:
+    items:
+      - description: board XO clock
+
+  clock-names:
+    items:
+      - const: xo
+
+  operating-points-v2: true
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    a73pll: clock@b116000 {
+            compatible = "qcom,ipq9574-a73pll";
+            reg = <0x0b116000 0x40>;
+            #clock-cells = <0>;
+            clocks = <&xo_board_clk>;
+            clock-names = "xo";
+    };
-- 
2.17.1