Received: by 2002:a05:6358:a55:b0:ec:fcf4:3ecf with SMTP id 21csp1269891rwb; Fri, 13 Jan 2023 09:58:29 -0800 (PST) X-Google-Smtp-Source: AMrXdXuSMoi7YKVwpqaTg9vQ3gsM4ZkAjUyd4hYTXNUCZXSF2W5bQvu4CPNqvEtUHsewdvvPVOcV X-Received: by 2002:a17:906:57c1:b0:84d:4646:1848 with SMTP id u1-20020a17090657c100b0084d46461848mr21630250ejr.44.1673632708977; Fri, 13 Jan 2023 09:58:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673632708; cv=none; d=google.com; s=arc-20160816; b=Npxq9PEGBqMUuNLSWv1llbcZCEY3W7DGye6HoDHzNgqafSmGFUwU17SMePlYz0E98Y 4JI844bC6eP2PaSLA59ir/xDReXQBZ4YrH2MyTaCxkvaD7M/0Am8/2NoCMQUmLBeCpJp 5L9AXaYJkx2j2DOVwQyY/Khg7wg7JD/WHWYFnHQAef2Bx0e/5mS2f7Pn8Z/c/A8QGU7e QtrNwqDpPw/nxDThqvIkImMrbGOHi+J9gBJ+26erv6MWXxlnCNCIHZ5xw6V5ZkG+KPXy mb3umYIRSjXGpDKex3OFD1zfeu6J2+Dua4RTY187yIAudZJDjVDBfXEYW4p/Sku0ADib q6gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WHb8JTG3jsfwmAuZTWMSdfupMqv5Vu5ZnFpJqUtjDgw=; b=xuY8QYxSPDl10ujrSVufewxpjz4RtT9yH4wzYmP2kmb5qx1hSIEpNimoa0ulScilBf ywPOLDl1mtZtaw3iGAPpGN484fcKs+XG4aJqBrrhSavylBTsP5yreNByu2MnD4t6R7hp UrqrYgmP9Hi+ThFKSOA4F2CClpXVIGPMzXuE10R9cSZWc09809nOU+1Fv9ujp1J8vd2v 8QQ5CPxVx3TG8NSdN5mrg5fuC0h/6ZpaIoGeFJ89ozwIZcLrng0/ns2FTr2QOCIGBDmT rn/IRI55VxtrieyqO6MwIuEBf1z/ddsiyFYdttW/h/Itkd59YLeuaJAcmOJGTCNjE7gr TfYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=n+hglCmV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nb29-20020a1709071c9d00b0084c04d15e97si12080976ejc.499.2023.01.13.09.58.10; Fri, 13 Jan 2023 09:58:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=n+hglCmV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230374AbjAMRoD (ORCPT + 53 others); Fri, 13 Jan 2023 12:44:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230132AbjAMRnL (ORCPT ); Fri, 13 Jan 2023 12:43:11 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF93E6C051 for ; Fri, 13 Jan 2023 09:29:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673630974; x=1705166974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=13rDlRrWtSaYMdkY5P+PHEVg2xd/vRWLrnc0TqjnqHE=; b=n+hglCmV/37XU2riL74OQcmOZM991MxKDJpEGn5ml/qbCDfK3Sbt8ZLd Uzl6cZcT9PyNV6/RK0+4dRghKO8Q6R1UAJCn8AZQtc5CQ9CN4ZZA42Dj1 Mt9s8uyu2U8oRkHCAuaJNIXbleg8zubpqXrTFJfBxzJMcNh/iF93+QGVC G2AUYwSM/mLrcfelYbdbnNqZIIgxeTl9S8nVRpkEXpRH+9aBybiKOaVfR ca+ecaWqEkpHOoVShHTZq25v9dqlBZbrrlxtTb/MyLskc5NXj8SrvrrLk krM2SPwYNFjfsuygVYb28zzUbv6pY6dnvGfDbAXktY0V73cK4vCWCvbEZ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="304430038" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="304430038" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 09:29:33 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10589"; a="766089937" X-IronPort-AV: E=Sophos;i="5.97,214,1669104000"; d="scan'208";a="766089937" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2023 09:29:33 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: Ashok Raj , LKML , x86 , Ingo Molnar , Tony Luck , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper Subject: [PATCH v1 Part2 5/5] x86/microcode: Provide an option to override minrev enforcement Date: Fri, 13 Jan 2023 09:29:20 -0800 Message-Id: <20230113172920.113612-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230113172920.113612-1-ashok.raj@intel.com> References: <20230113172920.113612-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Minimum Required Revision (minrev) is enforced strictly. All new patches will have a minrev that is not zero. But there might be a transition time for some that need this enforcement to be relaxed. When the override is enabled, the kernel will be tainted. Provide a debugfs variable to override the minrev enforcement. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper --- This patch is optional. --- arch/x86/include/asm/microcode.h | 2 ++ arch/x86/kernel/cpu/microcode/core.c | 13 ++++++++++++- arch/x86/kernel/cpu/microcode/intel.c | 8 ++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 3d48143e84a9..d82f22d50ebd 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -16,6 +16,8 @@ struct ucode_patch { extern struct list_head microcode_cache; +extern bool override_minrev; + struct cpu_signature { unsigned int sig; unsigned int pf; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 446ddf3fcc29..5ed60c6c8e8d 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,9 @@ #define DRIVER_VERSION "2.2" static struct microcode_ops *microcode_ops; +static struct dentry *dentry_ucode; static bool dis_ucode_ldr = true; +bool override_minrev; bool initrd_gone; @@ -497,7 +500,11 @@ static ssize_t reload_store(struct device *dev, pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); ret = -EINVAL; - goto put; + + if (!override_minrev) + goto put; + + pr_err("Overriding minrev\n"); } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); @@ -688,7 +695,11 @@ static int __init microcode_init(void) cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", mc_cpu_online, mc_cpu_down_prep); + dentry_ucode = debugfs_create_dir("microcode", NULL); + debugfs_create_bool("override_minrev", 0644, dentry_ucode, &override_minrev); + pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); + pr_info("Override minrev %s\n", override_minrev ? "enabled" : "disabled"); return 0; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 68a3c5569cd2..172e1f166844 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -141,6 +141,14 @@ static int is_lateload_safe(struct microcode_header_intel *mc_header) { struct ucode_cpu_info uci; + /* + * If minrev is bypassed via debugfs, then allow late-load. + */ + if (override_minrev) { + pr_info("Bypassing minrev enforcement via debugfs\n"); + return 0; + } + /* * When late-loading, ensure the header declares a minimum revision * required to perform a late-load. -- 2.34.1