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Date:   Mon, 16 Jan 2023 08:52:21 +0800
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Subject: Re: [PATCH V2 5/7] arm64: dts: imx93: add FEC support
Content-Language: en-US
To:     Clark Wang <xiaoning.wang@nxp.com>, wei.fang@nxp.com,
        shenwei.wang@nxp.com, davem@davemloft.net, edumazet@google.com,
        kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org,
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Cc:     linux-imx@nxp.com, kernel@pengutronix.de, netdev@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
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References: <20230113033347.264135-1-xiaoning.wang@nxp.com>
 <20230113033347.264135-6-xiaoning.wang@nxp.com>
From:   Peng Fan <peng.fan@oss.nxp.com>
In-Reply-To: <20230113033347.264135-6-xiaoning.wang@nxp.com>
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On 1/13/2023 11:33 AM, Clark Wang wrote:
> Add FEC node for imx93 platform.
> 
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
> New patch added in V2 for FEC
> ---
>   arch/arm64/boot/dts/freescale/imx93.dtsi | 26 ++++++++++++++++++++++++
>   1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index ff2253cb7d4a..12e0350ad35a 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -586,6 +586,32 @@ eqos: ethernet@428a0000 {
>   				status = "disabled";
>   			};
>   
> +			fec: ethernet@42890000 {
> +				compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
> +				reg = <0x42890000 0x10000>;
> +				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX93_CLK_ENET1_GATE>,
> +					 <&clk IMX93_CLK_ENET1_GATE>,
> +					 <&clk IMX93_CLK_ENET_TIMER1>,
> +					 <&clk IMX93_CLK_ENET_REF>,
> +					 <&clk IMX93_CLK_ENET_REF_PHY>;
> +				clock-names = "ipg", "ahb", "ptp",
> +					      "enet_clk_ref", "enet_out";
> +				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
> +						  <&clk IMX93_CLK_ENET_REF>,
> +						  <&clk IMX93_CLK_ENET_REF_PHY>;
> +				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> +							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
> +							 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
> +				assigned-clock-rates = <100000000>, <250000000>, <50000000>;
> +				fsl,num-tx-queues = <3>;
> +				fsl,num-rx-queues = <3>;
> +				status = "disabled";
> +			};
> +
>   			usdhc3: mmc@428b0000 {
>   				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
>   				reg = <0x428b0000 0x10000>;