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From:   Pierluigi Passaro <pierluigi.p@variscite.com>
To:     Andrew Lunn <andrew@lunn.ch>,
        Pierluigi Passaro <pierluigi.passaro@gmail.com>
CC:     Lars-Peter Clausen <lars@metafoo.de>,
        "hkallweit1@gmail.com" <hkallweit1@gmail.com>,
        "linux@armlinux.org.uk" <linux@armlinux.org.uk>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "edumazet@google.com" <edumazet@google.com>,
        "kuba@kernel.org" <kuba@kernel.org>,
        "pabeni@redhat.com" <pabeni@redhat.com>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Eran Matityahu <eran.m@variscite.com>,
        Nate Drude <Nate.D@variscite.com>,
        Francesco Ferraro <francesco.f@variscite.com>
Subject: Re: [PATCH] net: mdio: force deassert MDIO reset signal
Thread-Topic: [PATCH] net: mdio: force deassert MDIO reset signal
Thread-Index: AQHZKPvgQPO0npisDkSvgN3jEdgJF66fthyAgABQ/YCAAAm5gIAAG3CAgACcr+s=
Date:   Mon, 16 Jan 2023 09:44:01 +0000
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On Mon, Jan 16, 2023 at 1:11 AM Andrew Lunn <andrew@lunn.ch> wrote:=0A=
> > IMHO, since the framework allows defining the reset GPIO, it does not s=
ound=0A=
> > reasonable to manage it only after checking if the PHY can communicate:=
=0A=
> > if the reset is asserted, the PHY cannot communicate at all.=0A=
> > This patch just ensures that, if the reset GPIO is defined, it's not as=
serted=0A=
> > while checking the communication.=0A=
>=0A=
> The problem is, you are only solving 1/4 of the problem. What about=0A=
> the clock the PHY needs? And the regulator, and the linux reset=0A=
> controller? And what order to do enable these, and how long do you=0A=
> wait between each one?=0A=
>=0A=
Interesting point of view: I was thinking about solving one of 4 problems ;=
)=0A=
This problem affects all the platforms using the reset GPIO without=0A=
ensuring that either u-boot or the HW put a pull-up on it.=0A=
In our test, the problem is reproducible simply setting the reset to 0 from=
=0A=
u-boot and then use the GPIO reset as designed in the MDIO framework.=0A=
Is this approach=A0reasonable or a comprehensive=A0solution is expected to=
=0A=
cover all additional HW actors (clocks, regulators, ...) ?>=0A=
> And why are you solving this purely for Ethernet PHYs when the same=0A=
> problem probably affects other sorts of devices which have reset=0A=
> GPIOs, regulators and clocks? It looks like MMC/SDIO devices have a=0A=
> similar problem.=0A=
>=0A=
> https://lwn.net/Articles/867740/=0A=
>=0A=
> As i said, i've not been following this work. Has it got anywhere? Can=0A=
> ethernet PHYs use it?=0A=
>=0A=
> =A0 =A0 =A0 =A0 =A0Andrew=0A=
I'm not that familiar with the article's implications, but it sounds like a=
=0A=
partial redesign of the framework is needed.=0A=
I'm not sure this is the real point.=0A=
Let's refer to I2C/SPI/USB busses, the sequence is something like=0A=
- probe and setup the bus=0A=
- once the bus is up & running, start probing the connected slaves=0A=
Apparently, in the MDIO framework there's an excessive coupling=0A=
between the MDIO bus and the PHYs.=0A=
I can't really understand why the MDIO bus must check the PHY presence.=0A=
Other busses try the communication only while probing the slaves,=0A=
never before.=