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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ds5-20020a170907724500b0084514612c2bsi34581984ejc.610.2023.01.16.09.49.45; Mon, 16 Jan 2023 09:50:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=O5p1zKS0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233786AbjAPQnN (ORCPT + 50 others); Mon, 16 Jan 2023 11:43:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233728AbjAPQm3 (ORCPT ); Mon, 16 Jan 2023 11:42:29 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 972CF38B5A; Mon, 16 Jan 2023 08:30:39 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30GGUP8q057885; Mon, 16 Jan 2023 10:30:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1673886625; bh=O2Ejt62mxUfx3tdgkGy7b2vFDYAAKe8GIb3qDpu9Tkg=; h=Date:To:CC:References:From:Subject:In-Reply-To; b=O5p1zKS05dBbPWH2OwB072suoBV4NmioQWqawQVR3rXXSC3o4sSX6FpvNkeU1bSNc bJmiOPgyq/YeF50tQoEnvQ9XIRCUU32s+cZ7Z19Fb34Pi8/qKugBFvG4rxwiyPYPWs ipS3THuMt6DhlwX3zXzDIm0nq5mncsMf4iPGLIok= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30GGUPk7053486 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Jan 2023 10:30:25 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 16 Jan 2023 10:30:25 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 16 Jan 2023 10:30:25 -0600 Received: from [10.250.234.92] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30GGUJFM063429; Mon, 16 Jan 2023 10:30:20 -0600 Message-ID: <4d7ac24a-0a35-323c-045c-cc5b3d3c715a@ti.com> Date: Mon, 16 Jan 2023 22:00:18 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Content-Language: en-US To: Roger Quadros , Siddharth Vadapalli CC: , , , , , , , , , , , , , , References: <20230111114429.1297557-1-s-vadapalli@ti.com> <20230111114429.1297557-6-s-vadapalli@ti.com> <6ae650c9-d68d-d2fc-8319-b7784cd2a749@kernel.org> <2007adb5-0980-eee3-8d2f-e30183cf408e@kernel.org> From: Vignesh Raghavendra Subject: Re: [PATCH net-next 5/5] arm64: dts: ti: k3-am625-sk: Add cpsw3g cpts PPS support In-Reply-To: <2007adb5-0980-eee3-8d2f-e30183cf408e@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/01/23 9:35 pm, Roger Quadros wrote: >>>> diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>> index 4f179b146cab..962a922cc94b 100644 >>>> --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>> +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>> @@ -366,6 +366,10 @@ &cpsw3g { >>>> pinctrl-names = "default"; >>>> pinctrl-0 = <&main_rgmii1_pins_default >>>> &main_rgmii2_pins_default>; >>>> + >>>> + cpts@3d000 { >>>> + ti,pps = <2 1>; >>>> + }; >>>> }; >>>> >>>> &cpsw_port1 { >>>> @@ -464,3 +468,19 @@ partition@3fc0000 { >>>> }; >>>> }; >>>> }; >>>> + >>>> +#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) >>> Should this go in ./include/dt-bindings/pinctrl/k3.h ? >>> That way every board DT file doesn't have to define it. >>> >>> The name should be made more platform specific. >>> e.g. K3_TS_OFFSET if it is the same for all K3 platforms. >>> If not then please add Platform name instead of K3. >> The offsets are board specific. If it is acceptable, I will add board specific >> macro for the TS_OFFSET definition in the ./include/dt-bindings/pinctrl/k3.h >> file. Please let me know. > If it is board specific then it should remain in the board file. The values you pass to macro maybe board specific. But the macro definition itself same for a given SoC right? Also, is its same across K3 family ? Please use SoC specific prefix like AM62X_TS_OFFSET() or K3_TS_OFFSET() accordingly. Regards Vignesh