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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] net: mtk_sgmii: implement mtk_pcs_ops Message-ID: References: <87o7qy39v5.fsf@miraculix.mork.no> <87h6wq35dn.fsf@miraculix.mork.no> <87bkmy33ph.fsf@miraculix.mork.no> <875yd630cu.fsf@miraculix.mork.no> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <875yd630cu.fsf@miraculix.mork.no> Sender: Russell King (Oracle) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 16, 2023 at 05:33:53PM +0100, Bj?rn Mork wrote: > "Russell King (Oracle)" writes: > > > On Mon, Jan 16, 2023 at 04:21:30PM +0100, Bj?rn Mork wrote: > >> [ 54.539438] mtk_soc_eth 15100000.ethernet wan: Link is Down > >> [ 56.619937] mtk_sgmii_select_pcs: id=1 > >> [ 56.623690] mtk_pcs_config: interface=4 > >> [ 56.627511] offset:0 0x140 > >> [ 56.627513] offset:4 0x4d544950 > >> [ 56.630215] offset:8 0x20 > >> [ 56.633340] forcing AN > >> [ 56.638292] mtk_pcs_config: rgc3=0x0, advertise=0x1 (changed), link_timer=1600000, sgm_mode=0x103, bmcr=0x1000, use_an=1 > >> [ 56.649226] mtk_pcs_link_up: interface=4 > >> [ 56.653135] offset:0 0x81140 > >> [ 56.653137] offset:4 0x4d544950 > >> [ 56.656001] offset:8 0x1 > >> [ 56.659137] mtk_soc_eth 15100000.ethernet wan: Link is Up - 1Gbps/Full - flow control rx/tx > > > > Thanks - there seems to be something weird with the bmcr value printed > > above in the mtk_pcs_config line. > > > > You have bmcr=0x1000, but the code sets two bits - SGMII_AN_RESTART and > > SGMII_AN_ENABLE which are bits 9 and 12, so bmcr should be 0x1200, not > > 0x1000. Any ideas why? > > No, not really > > > Can you also hint at what the bits in the PHY register you quote mean > > please? > > This could very well be a red herring. It's the only difference I've > been able to spot, but I have no idea what it means. > > This is an attempt at reformatting the pdf tables for email. Hope it's > readable: I found the document for the PHY at: https://assets.maxlinear.com/web/documents/617792_gpy212b1vc_gpy212c0vc_ds_rev1.3.pdf It seems as I suspected, the PHY has not completed SGMII AN. Please can you read register 8 when operating at 1G speeds as well (VSPEC1_SGMII_CTRL)? Thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!