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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Yipeng Zou <zouyipeng@huawei.com>, Marc Zyngier <maz@kernel.org>
Cc:     linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        hewenliang4@huawei.com, chris.zjh@huawei.com, liaochang1@huawei.com
Subject: Re: [RFC PATCH] irqchip/gic-v3: wait irq done to set affinity
In-Reply-To: <89553b60-c5dc-76ad-67a4-594858ebedee@huawei.com>
References: <20230106082136.68501-1-zouyipeng@huawei.com>
 <86pmbrop11.wl-maz@kernel.org>
 <89553b60-c5dc-76ad-67a4-594858ebedee@huawei.com>
Date:   Tue, 17 Jan 2023 10:38:41 +0100
Message-ID: <87tu0plcv2.ffs@tglx>
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On Mon, Jan 09 2023 at 20:26, Yipeng Zou wrote:
> =E5=9C=A8 2023/1/6 19:55, Marc Zyngier =E5=86=99=E9=81=93:
> index 973ede0197e3..fad08ccb7fd9 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1667,6 +1667,9 @@ static int its_set_affinity(struct irq_data *d,=20
> const struct cpumask *mask_val,
>
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* don't set the affinity whe=
n the target cpu is same as=20
> current one */
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (cpu !=3D prev_cpu) {
> +
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 // wait irq done on all cpus
> +

There is no way to wait here. The caller holds the interrupt descriptor
lock.

If this is really an issue for LPI, then the only way to deal with that
is CONFIG_GENERIC_PENDING_IRQ, which delays the affinity change to
interrupt context

Why on earth must all the known hardware mistakes be repeated over and
over?

Thanks,

        tglx