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Date:   Tue, 17 Jan 2023 14:44:46 +0530
From:   Pavan Kondeti <quic_pkondeti@quicinc.com>
To:     Abel Vesa <abel.vesa@linaro.org>
CC:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        "Sai Prakash Ranjan" <quic_saipraka@quicinc.com>
Subject: Re: [PATCH v9 02/10] arm64: dts: qcom: Add base SM8550 dtsi
Message-ID: <20230117091446.GA3704192@hu-pkondeti-hyd.qualcomm.com>
References: <20230106201047.337409-1-abel.vesa@linaro.org>
 <20230106201047.337409-3-abel.vesa@linaro.org>
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On Fri, Jan 06, 2023 at 10:10:39PM +0200, Abel Vesa wrote:
> +		cpufreq_hw: cpufreq@17d91000 {
> +			compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> +			reg = <0 0x17d91000 0 0x1000>,
> +			      <0 0x17d92000 0 0x1000>,
> +			      <0 0x17d93000 0 0x1000>;
> +			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
> +			#freq-domain-cells = <1>;
> +		};

Currently, I am seeing available frequencies as 2x of the original
frequencies. This is observed for all CPUs. The xo source should be bi_tcxo here.
I will send a patch on top of qcom/linux : arm64-for-6.3 branch.

Thanks,
Pavan