Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <96a20619-6253-3380-9a25-5f8d8b6a47cf@quicinc.com>
Date:   Thu, 19 Jan 2023 11:32:39 +0530
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101
 Thunderbird/91.11.0
From:   Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Subject: Re: [RESEND v3 4/4] clk: qcom: lpasscc-sc7280: Add resets for
 audioreach
To:     Stephen Boyd <swboyd@chromium.org>, <agross@kernel.org>,
        <andersson@kernel.org>, <broonie@kernel.org>,
        <konrad.dybcio@somainline.org>,
        <krzysztof.kozlowski+dt@linaro.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <mturquette@baylibre.com>,
        <quic_plai@quicinc.com>, <quic_rohkumar@quicinc.com>,
        <robh+dt@kernel.org>
References: <1672849297-3116-1-git-send-email-quic_srivasam@quicinc.com>
 <1672849297-3116-5-git-send-email-quic_srivasam@quicinc.com>
 <CAE-0n51AZCa9K_uY=ikTLqV-g_MsSA6Lv=Zq1LMrF-wVhR8_pg@mail.gmail.com>
 <6cea0a3f-08de-47d5-99d1-74b0d8c7b732@quicinc.com>
 <CAE-0n52ahKMzk0ho5jG1wxebm3ZE+Wfu_BunCaTR1WhN+J5jpw@mail.gmail.com>
Content-Language: en-US
Organization: Qualcomm
In-Reply-To: <CAE-0n52ahKMzk0ho5jG1wxebm3ZE+Wfu_BunCaTR1WhN+J5jpw@mail.gmail.com>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 8bit
Precedence: bulk


On 1/13/2023 1:05 AM, Stephen Boyd wrote:
> Quoting Srinivasa Rao Mandadapu (2023-01-11 23:53:23)
>> On 1/12/2023 2:54 AM, Stephen Boyd wrote:
>> Thanks for your time Stephen!!!
>>> Quoting Srinivasa Rao Mandadapu (2023-01-04 08:21:37)
>>>> diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
>>>> index 85dd5b9..1efb72d 100644
>>>> --- a/drivers/clk/qcom/lpasscc-sc7280.c
>>>> +++ b/drivers/clk/qcom/lpasscc-sc7280.c
>>>> @@ -102,6 +104,18 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
>>>>           .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
>>>>    };
>>>>
>>>> +static const struct qcom_reset_map lpass_cc_sc7280_resets[] = {
>>>> +       [LPASS_AUDIO_SWR_RX_CGCR] =  { 0xa0, 1 },
>>>> +       [LPASS_AUDIO_SWR_TX_CGCR] =  { 0xa8, 1 },
>>>> +       [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
>>> Why are we adding these resets again? These are already exposed in
>>> lpassaudiocc-sc7280.c
>> As explained in previous versions, legacy path nodes are not being used
>> in ADSP based platforms, due to conflicts.
> What is legacy path nodes?
Legacy path nodes are for ADSP bypass use case such as nodes 
lpass_audiocc, lpass_core, etc.
>
>> Hence lpasscc node alone being used exclusively in ADSP based solution,
>> resets are added.
> I think I understand..
>
>> In probe also, these reset controls are enabled based on
>> "qcom,adsp-pil-mode" property.
>>
> but now I'm super confused! Please help me! We shouldn't have two
> different device nodes for the same physical hardware registers.
> Instead, we should have one node. The "qcom,adsp-pil-mode" property was
> supposed to indicate the different mode of operation.
>
> Maybe the audio clk and reset drivers on sc7280 are duplicating each
> other and one of them can be removed?

Yes agreed, that for controlling same registers from two different 
drivers is not good solution.

But, when we are validating ADSP solution, we have seen issues like ADSP 
is not coming out of reset with the existing bypass mode

clock drivers(lpassaudiocc_sc7280.c and lpasscoreecc_sc7280.c) enabled.

As per your suggestion, will try to address that  issues with 
"qcom,adsp-pil-mode" property and avoid duplicating reset control code

in lpasscc driver(lpasscc_sc7280.c).