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Message-ID: <8ae4469e-ed2c-5019-605b-013a49af77ea@gmail.com>
Date:   Thu, 19 Jan 2023 17:08:48 +0100
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Subject: Re: [PATCH v6 1/4] dt-bindings: arm: mediatek: migrate MT8195
 vppsys0/1 to mtk-mmsys driver
Content-Language: en-US
To:     Moudy Ho <moudy.ho@mediatek.com>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>
Cc:     devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
        Project_Global_Chrome_Upstream_Group@mediatek.com
References: <20230118031509.29834-1-moudy.ho@mediatek.com>
 <20230118031509.29834-2-moudy.ho@mediatek.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
In-Reply-To: <20230118031509.29834-2-moudy.ho@mediatek.com>
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On 18/01/2023 04:15, Moudy Ho wrote:
> MT8195 VPPSYS 0/1 should be probed from mtk-mmsys driver to
> populate device by platform_device_register_data then start
> its own clock driver.
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

Stephen, if you want I can take 1/4 and 3/4 through my tree. 3/4 shouldn't be a 
problem, not sure about this patch. In any case if you want me to do so, I'd 
need a Acked-by from you.

Regards,
Matthias

> ---
>   .../arm/mediatek/mediatek,mt8195-clock.yaml      | 16 ----------------
>   1 file changed, 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> index 17fcbb45d121..d62d60181147 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> @@ -28,11 +28,9 @@ properties:
>             - mediatek,mt8195-imp_iic_wrap_s
>             - mediatek,mt8195-imp_iic_wrap_w
>             - mediatek,mt8195-mfgcfg
> -          - mediatek,mt8195-vppsys0
>             - mediatek,mt8195-wpesys
>             - mediatek,mt8195-wpesys_vpp0
>             - mediatek,mt8195-wpesys_vpp1
> -          - mediatek,mt8195-vppsys1
>             - mediatek,mt8195-imgsys
>             - mediatek,mt8195-imgsys1_dip_top
>             - mediatek,mt8195-imgsys1_dip_nr
> @@ -92,13 +90,6 @@ examples:
>           #clock-cells = <1>;
>       };
>   
> -  - |
> -    vppsys0: clock-controller@14000000 {
> -        compatible = "mediatek,mt8195-vppsys0";
> -        reg = <0x14000000 0x1000>;
> -        #clock-cells = <1>;
> -    };
> -
>     - |
>       wpesys: clock-controller@14e00000 {
>           compatible = "mediatek,mt8195-wpesys";
> @@ -120,13 +111,6 @@ examples:
>           #clock-cells = <1>;
>       };
>   
> -  - |
> -    vppsys1: clock-controller@14f00000 {
> -        compatible = "mediatek,mt8195-vppsys1";
> -        reg = <0x14f00000 0x1000>;
> -        #clock-cells = <1>;
> -    };
> -
>     - |
>       imgsys: clock-controller@15000000 {
>           compatible = "mediatek,mt8195-imgsys";