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Date:   Thu, 19 Jan 2023 10:12:21 -0800
From:   Bjorn Andersson <quic_bjorande@quicinc.com>
To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
CC:     Rob Clark <robdclark@gmail.com>,
        Abhinav Kumar <quic_abhinavk@quicinc.com>,
        Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Kalyan Thota <quic_kalyant@quicinc.com>,
        Jessica Zhang <quic_jesszhan@quicinc.com>,
        "Kuogee Hsieh" <quic_khsieh@quicinc.com>,
        Johan Hovold <johan+linaro@kernel.org>,
        Sankeerth Billakanti <quic_sbillaka@quicinc.com>,
        <linux-arm-msm@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
        <freedreno@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 10/12] arm64: dts: qcom: sc8280xp: Define some of the
 display blocks
Message-ID: <20230119181221.GA3951310@hu-bjorande-lv.qualcomm.com>
References: <20221207220012.16529-1-quic_bjorande@quicinc.com>
 <20221207220012.16529-11-quic_bjorande@quicinc.com>
 <6e7b1518-0dd5-59a6-128a-e3c3c194bf52@linaro.org>
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In-Reply-To: <6e7b1518-0dd5-59a6-128a-e3c3c194bf52@linaro.org>
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On Wed, Jan 18, 2023 at 04:58:26AM +0200, Dmitry Baryshkov wrote:
> On 08/12/2022 00:00, Bjorn Andersson wrote:
> > From: Bjorn Andersson <bjorn.andersson@linaro.org>
> > 
> > Define the display clock controllers, the MDSS instances, the DP phys
> > and connect these together.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> > ---
> > 
> > Changes since v4:
> > - None
> > 
> >   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +++++++++++++++++++++++++
> >   1 file changed, 838 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index 9f3132ac2857..c2f186495506 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -4,6 +4,7 @@
> >    * Copyright (c) 2022, Linaro Limited
> >    */
> > +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
> >   #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
> >   #include <dt-bindings/clock/qcom,rpmh.h>
> >   #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> > @@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 {
> >   			status = "disabled";
> >   		};
> > +		mdss1_dp0_phy: phy@8909a00 {
> > +			compatible = "qcom,sc8280xp-dp-phy";
> > +			reg = <0 0x08909a00 0 0x19c>,
> > +			      <0 0x08909200 0 0xec>,
> > +			      <0 0x08909600 0 0xec>,
> > +			      <0 0x08909000 0 0x1c8>;
> > +
> > +			clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > +				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> > +			clock-names = "aux", "cfg_ahb";
> > +
> > +			power-domains = <&rpmhpd SC8280XP_MX>;
> > +
> > +			#clock-cells = <1>;
> > +			#phy-cells = <0>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		mdss1_dp1_phy: phy@890ca00 {
> > +			compatible = "qcom,sc8280xp-dp-phy";
> > +			reg = <0 0x0890ca00 0 0x19c>,
> > +			      <0 0x0890c200 0 0xec>,
> > +			      <0 0x0890c600 0 0xec>,
> > +			      <0 0x0890c000 0 0x1c8>;
> > +
> > +			clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> > +				 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> > +			clock-names = "aux", "cfg_ahb";
> > +
> > +			power-domains = <&rpmhpd SC8280XP_MX>;
> > +
> > +			#clock-cells = <1>;
> > +			#phy-cells = <0>;
> > +
> > +			status = "disabled";
> > +		};
> > +
> >   		system-cache-controller@9200000 {
> >   			compatible = "qcom,sc8280xp-llcc";
> >   			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
> > @@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a800000 {
> >   			};
> >   		};
> > +		mdss0: display-subsystem@ae00000 {
> > +			compatible = "qcom,sc8280xp-mdss";
> > +			reg = <0 0x0ae00000 0 0x1000>;
> > +			reg-names = "mdss";
> > +
> > +			power-domains = <&dispcc0 MDSS_GDSC>;
> > +
> > +			clocks = <&gcc GCC_DISP_AHB_CLK>,
> > +				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> > +				 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
> > +			clock-names = "iface",
> > +				      "ahb",
> > +				      "core";
> > +
> > +			resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
> > +
> > +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <1>;
> > +
> > +			interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> > +					<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> > +			interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > +			iommus = <&apps_smmu 0x1000 0x402>;
> > +
> > +			status = "disabled";
> > +
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
> > +
> > +			mdss0_mdp: display-controller@ae01000 {
> > +				compatible = "qcom,sc8280xp-dpu";
> > +				reg = <0 0x0ae01000 0 0x8f000>,
> > +				      <0 0x0aeb0000 0 0x2008>;
> > +				reg-names = "mdp", "vbif";
> > +
> > +				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > +					 <&gcc GCC_DISP_SF_AXI_CLK>,
> > +					 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> > +					 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
> > +					 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
> > +					 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> > +				clock-names = "bus",
> > +					      "nrt_bus",
> > +					      "iface",
> > +					      "lut",
> > +					      "core",
> > +					      "vsync";
> > +
> > +				assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
> > +						  <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> > +				assigned-clock-rates = <460000000>,
> > +						       <19200000>;
> > +
> > +				operating-points-v2 = <&mdss0_mdp_opp_table>;
> > +				power-domains = <&rpmhpd SC8280XP_MMCX>;
> > +
> > +				interrupt-parent = <&mdss0>;
> > +				interrupts = <0>;
> > +
> > +				ports {
> > +					#address-cells = <1>;
> > +					#size-cells = <0>;
> > +
> > +					port@5 {
> > +						reg = <5>;
> > +						mdss0_intf5_out: endpoint {
> > +							remote-endpoint = <&mdss0_dp3_in>;
> > +						};
> > +					};
> > +
> > +					port@6 {
> > +						reg = <6>;
> > +						mdss0_intf6_out: endpoint {
> > +							remote-endpoint = <&mdss0_dp2_in>;
> > +						};
> > +					};
> > +				};
> 
> This now fails with:
> 
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: display-controller@ae01000:
> ports: 'port@0' is a required property
> 	From schema:
> Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dtb: display-controller@ae01000:
> Unevaluated properties are not allowed ('ports' was unexpected)
> 	From schema:
> Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
> 
> We do not map reg ids to INTF indices. So, unless you plan to change that,
> could you please change these to port@0 / port@1 ?
> 

Too bad, I liked the fact that I gave these numbers any form of meaning.
I guess we can change it to just be an arbitrary index, and keep the
intf-information in the label...

Regards,
Bjorn

> [skipped the rest]
> 
> -- 
> With best wishes
> Dmitry
>