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Date:   Fri, 20 Jan 2023 10:39:12 +0800
From:   Xu Yilun <yilun.xu@intel.com>
To:     matthew.gerlach@linux.intel.com
Cc:     hao.wu@intel.com, russell.h.weight@intel.com,
        basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
        mdf@kernel.org, linux-fpga@vger.kernel.org,
        linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
        tianfei.zhang@intel.com, corbet@lwn.net,
        gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
        jirislaby@kernel.org, geert+renesas@glider.be,
        andriy.shevchenko@linux.intel.com,
        niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
        johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com,
        marpagan@redhat.com, bagasdotme@gmail.com
Subject: Re: [PATCH v11 0/4] Enhance definition of DFH and use enhancements
 for UART driver
Message-ID: <Y8n+0OUxnDtDfJgG@yilunxu-OptiPlex-7050>
References: <20230115151447.1353428-1-matthew.gerlach@linux.intel.com>
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On 2023-01-15 at 07:14:43 -0800, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> This patchset enhances the definition of the Device Feature Header (DFH) used by
> the Device Feature List (DFL) bus and then uses the new enhancements in a UART
> driver.
> 
> The enhancements to the DFH includes the introduction of parameter blocks.
> Like PCI capabilities, the DFH parameter blocks further describe
> the hardware to software. In the case of the UART, the parameter blocks
> provide information for the interrupt, clock frequency, and register layout.
> 
> Duplication of code parsing of the parameter blocks in multiple DFL drivers
> is a concern. Using swnodes was considered to help minimize parsing code 
> duplication, but their use did not help the problem. Furthermore the highly
> changeable nature of FPGAs employing the DFL bus makes the use of swnodes
> inappropriate. 
> 
> Patch 1 updates the DFL documentation to describe the added functionality to DFH.
> 
> Patch 2 adds the definitions for DFHv1.
> 
> Patch 3 adds basic support for DFHv1. It adds functionality to parse parameter blocks
> and adds the functionality to parse the explicit location of a feature's register set.
> 
> Patch 4 adds a DFL UART driver that makes use of the new features of DFHv1.

Looks good to me and see Greg has taken this patchset.

Thanks,
Yilun

> 
> Basheer Ahmed Muddebihal (1):
>   fpga: dfl: Add DFHv1 Register Definitions
> 
> Matthew Gerlach (3):
>   Documentation: fpga: dfl: Add documentation for DFHv1
>   fpga: dfl: add basic support for DFHv1
>   tty: serial: 8250: add DFL bus driver for Altera 16550.
> 
>  Documentation/fpga/dfl.rst         | 119 ++++++++++++++
>  drivers/fpga/dfl.c                 | 245 +++++++++++++++++++++++------
>  drivers/fpga/dfl.h                 |  43 +++++
>  drivers/tty/serial/8250/8250_dfl.c | 167 ++++++++++++++++++++
>  drivers/tty/serial/8250/Kconfig    |  12 ++
>  drivers/tty/serial/8250/Makefile   |   1 +
>  include/linux/dfl.h                |   8 +
>  7 files changed, 544 insertions(+), 51 deletions(-)
>  create mode 100644 drivers/tty/serial/8250/8250_dfl.c
> 
> -- 
> 2.25.1
>