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From:   Sudeep Holla <sudeep.holla@arm.com>
To:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        linux-kernel@vger.kernel.org
Cc:     Sudeep Holla <sudeep.holla@arm.com>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Yong-Xuan Wang <yongxuan.wang@sifive.com>,
        ALKML <linux-arm-kernel@lists.infradead.org>,
        linux-riscv@lists.infradead.org,
        Pierre Gondois <pierre.gondois@arm.com>
Subject: [GIT PULL]  cacheinfo/arch_topology: Updates for v6.3
Date:   Fri, 20 Jan 2023 12:18:56 +0000
Message-Id: <20230120121856.1407369-1-sudeep.holla@arm.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Hi Greg,

Please pull !

It has been tested on RISC-V which is the main users outside of arm64.
The ACPI the RISC-V parts are acked-by the respective maintainers. All
the changes are in the -next for sometime and no issues reported at this
time.

Regards,
Sudeep

-->8

The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2:

  Linux 6.2-rc1 (2022-12-25 13:41:39 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git tags/archtopo-cacheinfo-updates-6.3

for you to fetch changes up to 198102c9103fc78d8478495971947af77edb05c1:

  cacheinfo: Fix shared_cpu_map to handle shared caches at different levels (2023-01-18 09:58:40 +0000)

----------------------------------------------------------------
cacheinfo and arch_topology updates for v6.3

The main change is to build the cache topology information for all
the CPUs from the primary CPU. Currently the cacheinfo for secondary CPUs
is created during the early boot on the respective CPU itself. Preemption
and interrupts are disabled at this stage. On PREEMPT_RT kernels, allocating
memory and even parsing the PPTT table for ACPI based systems triggers a:
  'BUG: sleeping function called from invalid context'

To prevent this bug, the cacheinfo is now allocated from the primary CPU
when preemption and interrupts are enabled and before booting secondary
CPUs. The cache levels/leaves are computed from DT/ACPI PPTT information
only, without relying on any architecture specific mechanism if done so
early.

The other minor change included here is to handle shared caches at
different levels when not all the CPUs on the system have the same
cache hierarchy.

----------------------------------------------------------------
Pierre Gondois (6):
      cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation
      cacheinfo: Return error code in init_of_cache_level()
      cacheinfo: Check 'cache-unified' property to count cache leaves
      ACPI: PPTT: Remove acpi_find_cache_levels()
      ACPI: PPTT: Update acpi_find_last_cache_level() to acpi_get_cache_info()
      arch_topology: Build cacheinfo from primary CPU

Yong-Xuan Wang (1):
      cacheinfo: Fix shared_cpu_map to handle shared caches at different levels

 arch/arm64/kernel/cacheinfo.c |  11 +--
 arch/riscv/kernel/cacheinfo.c |  42 -----------
 drivers/acpi/pptt.c           |  93 ++++++++++++++----------
 drivers/base/arch_topology.c  |  12 +++-
 drivers/base/cacheinfo.c      | 161 +++++++++++++++++++++++++++++++++++-------
 include/linux/cacheinfo.h     |  11 ++-
 6 files changed, 213 insertions(+), 117 deletions(-)