Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 214DFC38142 for ; Mon, 23 Jan 2023 13:21:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231607AbjAWNVd (ORCPT ); Mon, 23 Jan 2023 08:21:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230352AbjAWNVb (ORCPT ); Mon, 23 Jan 2023 08:21:31 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5B9E25286 for ; Mon, 23 Jan 2023 05:21:27 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id hw16so30325065ejc.10 for ; Mon, 23 Jan 2023 05:21:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=YsXGq+84b3tFva8sx/OXAy3zCE5skYa0ofpr2MBER4c=; b=eRDEYhOIGJ103mS6oZnJoO+6Moo0rdjkBf0TOJ5mG0TBUOIxJc/CtJMsqHf7Tn6UuH sULITttpVPB4z/TZl9rXOV5TH2C9xOTHn1+1l7IajvYiAjGBhQeFPicvAMZsDe+v2ZXy ze6kRY+UwbVsCacMyfFQoCs85JCLULvRBsssHbCUgu8nvfAGuHN9ADc+nAGR6+7b351U lVusB2tp+v8OXfrGP2lIQY1AAFlwYo6vmzoVGHg/xOX3cuuZh1rmgGhSYe/yOAXJhqes jLuwg5Gqcwr/EmudOw+AaKZtN/saCTd/WXyVp5aVGTbflmbm2O9J+vZQomtTg4YRRlCk ObVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YsXGq+84b3tFva8sx/OXAy3zCE5skYa0ofpr2MBER4c=; b=Rr6h7KZb1OPpuk+MuFzZwDKccxiYPo00VSnxC+gNMJyHF4JZE4UieBG+TuIHgcWwHp X2t9/Fo8IvdXBiQhPgg1CX6WFn0ee4bNsjRG5H2P3kecKHCJ6ZT74aRsNS42R6cklIQ+ Re5Pj6reiLeCZVZoPw/ICxwSq50hi91N9bDCBlFQKvCwCfQfTQYIdyPGu3gKMfeTtUFa 9iayVzVF/BdjF2CD98cSTqgujph4ERf1uxEkt4Xd2B+EpAITxolNHMlmy4wPbDgfCjFt tpsUOijdKTovX7hqb5OKdwJsXdkTBTtj6geHU+OjeXUyM57lkx/Oc5eJulcp3c5qwQ4+ 6qsQ== X-Gm-Message-State: AFqh2kp7LcEksc/Oyua6SKN//JPlBpbUSI1hpf1+qCWeSSSeeIQR/RHW Zf2wkR8oehiTz3KAS2VpJ0RnpbzxdhkGb5Mr X-Google-Smtp-Source: AMrXdXvoSP7NORFjK/VvrRxhcuHbYeJ42QdKshHQmbhms89pHQrdDseSM67icmPAtdDWwLKfJneaAw== X-Received: by 2002:a17:907:cc03:b0:7c4:f8fb:6a27 with SMTP id uo3-20020a170907cc0300b007c4f8fb6a27mr34065026ejc.0.1674480086417; Mon, 23 Jan 2023 05:21:26 -0800 (PST) Received: from [192.168.1.101] (abxi24.neoplus.adsl.tpnet.pl. [83.9.2.24]) by smtp.gmail.com with ESMTPSA id p8-20020a17090653c800b00872c0bccab2sm9742043ejo.35.2023.01.23.05.21.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jan 2023 05:21:26 -0800 (PST) Message-ID: <8d07ba5e-6354-c2ba-bd09-5f8169732b55@linaro.org> Date: Mon, 23 Jan 2023 14:21:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH 3/3] ARM: dts: qcom: sdx65: Add Qcom SMMU-500 as the fallback for IOMMU node Content-Language: en-US To: Manivannan Sadhasivam , andersson@kernel.org, will@kernel.org, joro@8bytes.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, dmitry.baryshkov@linaro.org, stable@vger.kernel.org References: <20230123131931.263024-1-manivannan.sadhasivam@linaro.org> <20230123131931.263024-4-manivannan.sadhasivam@linaro.org> From: Konrad Dybcio In-Reply-To: <20230123131931.263024-4-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.01.2023 14:19, Manivannan Sadhasivam wrote: > SDX65 uses the Qcom version of the SMMU-500 IP. So use "qcom,smmu-500" > compatible as the fallback to the SoC specific compatible. > > Cc: # 5.19 > Fixes: 98187f7b74bf ("ARM: dts: qcom: sdx65: Enable ARM SMMU") > Signed-off-by: Manivannan Sadhasivam > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index b073e0c63df4..408c4b87d44b 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -455,7 +455,7 @@ pil-reloc@94c { > }; > > apps_smmu: iommu@15000000 { > - compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; > + compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > reg = <0x15000000 0x40000>; > #iommu-cells = <2>; > #global-interrupts = <1>;