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Mon, 23 Jan 2023 21:05:39 -0800 Envelope-to: git@amd.com, manikanta.guntupalli@amd.com, michal.simek@amd.com, shubhrajyoti.datta@amd.com, srinivas.goud@amd.com, manion05gk@gmail.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.3] (port=57529 helo=xhdvnc103.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1pKBV5-0000ob-A0; Mon, 23 Jan 2023 21:05:39 -0800 Received: by xhdvnc103.xilinx.com (Postfix, from userid 90444) id D4ADA1055B0; Tue, 24 Jan 2023 10:34:49 +0530 (IST) From: Manikanta Guntupalli To: , , , , CC: , , , , , Raviteja Narayanam Subject: [PATCH V3 4/9] i2c: xiic: Add wait for FIFO empty in send_tx Date: Tue, 24 Jan 2023 10:34:37 +0530 Message-ID: <1674536682-25278-5-git-send-email-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1674536682-25278-1-git-send-email-manikanta.guntupalli@amd.com> References: <1674536682-25278-1-git-send-email-manikanta.guntupalli@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3NAM02FT063:EE_|PH7PR02MB9290:EE_ X-MS-Office365-Filtering-Correlation-Id: 414b0937-788a-4b42-1d31-08dafdc8a814 X-MS-Exchange-SenderADCheck: 0 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 05:05:47.9648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 414b0937-788a-4b42-1d31-08dafdc8a814 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT063.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR02MB9290 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Raviteja Narayanam If the tx_half_empty interrupt comes first instead of tx_empty, STOP bit is generated even before all the bytes are transmitted out on the bus. STOP bit should be sent only after all the bytes in the FIFO are transmitted out of the FIFO. So wait until FIFO is empty before sending the STOP bit. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli Acked-by: Michal Simek --- drivers/i2c/busses/i2c-xiic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index edc64b79e293..57084696429c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) data |= XIIC_TX_DYN_STOP_MASK; } else { u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; + /* Write to CR to stop */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & -- 2.25.1