Message-ID: <8200e62a-0038-ae83-4c94-5059110d448e@arm.com>
Date:   Wed, 25 Jan 2023 10:21:09 +0000
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Subject: Re: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready
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To:     Yabin Cui <yabinc@google.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>
Cc:     Mike Leach <mike.leach@linaro.org>, coresight@lists.linaro.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        Leo Yan <leo.yan@linaro.org>
References: <20230109234312.2870846-1-yabinc@google.com>
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 <CAJ9a7Vj=e6rSbD9ONKDY1vyuxms161f-vp0Y4mxkQgpm1oz6uA@mail.gmail.com>
 <3eae7596-2ad8-1574-22d1-696184a3fa30@arm.com>
 <CALJ9ZPMaAQu4Pug-m-h6KM40pOofhpE1EkddBKz37WyBQGzEEA@mail.gmail.com>
 <CALJ9ZPNa41rO3iG1WhWAF5fBTUGF1ULUG62_zMTA0EwzGnw=8w@mail.gmail.com>
From:   James Clark <james.clark@arm.com>
In-Reply-To: <CALJ9ZPNa41rO3iG1WhWAF5fBTUGF1ULUG62_zMTA0EwzGnw=8w@mail.gmail.com>
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On 24/01/2023 20:09, Yabin Cui wrote:
> Ping for review. And I still can't reproduce it, even if I reduced the
> timeout to 2us and tried different workloads. Any suggestions for how
> to reproduce it?
> 

Hi Yabin,

I just found this in my kernel log files from a few days ago.

Jan 19 15:03:35 n1-sdp kernel: [865337.521413] coresight tmc_etr0:
timeout while waiting for completion of Manual Flush
Jan 19 15:03:35 n1-sdp kernel: [865337.529351] coresight tmc_etr0:
timeout while waiting for TMC to be Ready

This is on N1SDP, and I've only been running "normal" perf commands like:

  perf record -e cs_etm//k --  taskset -c 2 sleep 1
  perf record -e cs_etm//  -- stress -c 2 -t 1

I also haven't been able to reproduce it since

James