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Subject: Re: [PATCH] clk: ingenic: jz4760: Update M/N/OD calculation algorithm
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     list@opendingux.net, linux-mips@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        Paul Cercueil <paul@crapouillou.net>, stable@vger.kernel.org
To:     Michael Turquette <mturquette@baylibre.com>,
        Paul Cercueil <paul@crapouillou.net>
Date:   Wed, 25 Jan 2023 17:21:48 -0800
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Quoting Paul Cercueil (2022-12-14 04:37:04)
> The previous algorithm was pretty broken.
>=20
> - The inner loop had a '(m > m_max)' condition, and the value of 'm'
>   would increase in each iteration;
>=20
> - Each iteration would actually multiply 'm' by two, so it is not needed
>   to re-compute the whole equation at each iteration;
>=20
> - It would loop until (m & 1) =3D=3D 0, which means it would loop at most
>   once.
>=20
> - The outer loop would divide the 'n' value by two at the end of each
>   iteration. This meant that for a 12 MHz parent clock and a 1.2 GHz
>   requested clock, it would first try n=3D12, then n=3D6, then n=3D3, then
>   n=3D1, none of which would work; the only valid value is n=3D2 in this
>   case.
>=20
> Simplify this algorithm with a single for loop, which decrements 'n'
> after each iteration, addressing all of the above problems.
>=20
> Fixes: bdbfc029374f ("clk: ingenic: Add support for the JZ4760")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---

Applied to clk-fixes