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Subject: Re: [PATCH v1 03/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        Xingyu Wu <xingyu.wu@starfivetech.com>,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
To:     Emil Renner Berthing <kernel@esmil.dk>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Xingyu Wu <xingyu.wu@starfivetech.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Date:   Wed, 25 Jan 2023 18:33:54 -0800
User-Agent: alot/0.10
Precedence: bulk

Quoting Xingyu Wu (2023-01-19 18:44:37)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk=
/starfive/clk-starfive-jh7110-stg.c
> new file mode 100644
> index 000000000000..c2740f44e796
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH7110 System-Top-Group Clock Driver
> + *
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>

Is this include used? If not, please remove.

> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +
> +#include "clk-starfive-jh71x0.h"
> +
[...]
> +static int jh7110_stgcrg_probe(struct platform_device *pdev)
> +{
> +       struct jh71x0_clk_priv *priv;
> +       unsigned int idx;
> +       int ret;
> +
> +       priv =3D devm_kzalloc(&pdev->dev,
> +                           struct_size(priv, reg, JH7110_STGCLK_END),
> +                           GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       spin_lock_init(&priv->rmw_lock);
> +       priv->dev =3D &pdev->dev;
> +       priv->base =3D devm_platform_ioremap_resource(pdev, 0);
> +       if (IS_ERR(priv->base))
> +               return PTR_ERR(priv->base);
> +
> +       dev_set_drvdata(priv->dev, priv->base);
> +
> +       for (idx =3D 0; idx < JH7110_STGCLK_END; idx++) {
> +               u32 max =3D jh7110_stgclk_data[idx].max;
> +               struct clk_parent_data parents[4] =3D {};
> +               struct clk_init_data init =3D {
> +                       .name =3D jh7110_stgclk_data[idx].name,
> +                       .ops =3D starfive_jh71x0_clk_ops(max),
> +                       .parent_data =3D parents,
> +                       .num_parents =3D
> +                               ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CL=
K_MUX_SHIFT) + 1,
> +                       .flags =3D jh7110_stgclk_data[idx].flags,
> +               };
> +               struct jh71x0_clk *clk =3D &priv->reg[idx];
> +               unsigned int i;
> +
> +               for (i =3D 0; i < init.num_parents; i++) {
> +                       unsigned int pidx =3D jh7110_stgclk_data[idx].par=
ents[i];
> +
> +                       if (pidx < JH7110_STGCLK_END)
> +                               parents[i].hw =3D &priv->reg[pidx].hw;
> +                       else if (pidx =3D=3D JH7110_STGCLK_OSC)
> +                               parents[i].fw_name =3D "osc";
> +                       else if (pidx =3D=3D JH7110_STGCLK_HIFI4_CORE)
> +                               parents[i].fw_name =3D "hifi4_core";
> +                       else if (pidx =3D=3D JH7110_STGCLK_STG_AXIAHB)
> +                               parents[i].fw_name =3D "stg_axiahb";
> +                       else if (pidx =3D=3D JH7110_STGCLK_USB_125M)
> +                               parents[i].fw_name =3D "usb_125m";
> +                       else if (pidx =3D=3D JH7110_STGCLK_CPU_BUS)
> +                               parents[i].fw_name =3D "cpu_bus";
> +                       else if (pidx =3D=3D JH7110_STGCLK_HIFI4_AXI)
> +                               parents[i].fw_name =3D "hifi4_axi";
> +                       else if (pidx =3D=3D JH7110_STGCLK_NOCSTG_BUS)
> +                               parents[i].fw_name =3D "nocstg_bus";
> +                       else if (pidx =3D=3D JH7110_STGCLK_APB_BUS)
> +                               parents[i].fw_name =3D "apb_bus";

Can this be an array lookup instead of a pile of conditions?

	if (pidx < JH7110_STGCLK_END)
		...
	else
		parents[i].fw_name =3D fw_table[pidx - JH7110_STGCLK_END];

Or even better, don't use strings at all and just make the 'pidx' number
(possibly minus the end constant) be the 'clocks' property index that
you want.

> +               }
> +
> +               clk->hw.init =3D &init;
> +               clk->idx =3D idx;
> +               clk->max_div =3D max & JH71X0_CLK_DIV_MASK;
> +
> +               ret =3D devm_clk_hw_register(&pdev->dev, &clk->hw);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       ret =3D devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get=
, priv);
> +       if (ret)
> +               return ret;
> +
> +       return jh7110_reset_controller_register(priv, "reset-stg", 2);

Is this also devm-ified?