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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id b32-20020a05600c4aa000b003db0cab0844sm3956369wmp.40.2023.01.27.03.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 03:34:52 -0800 (PST) Date: Fri, 27 Jan 2023 12:34:51 +0100 From: Andrew Jones To: guoren@kernel.org Cc: arnd@arndb.de, palmer@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, tongtiangen@huawei.com, andrew@sifive.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: Re: [PATCH V2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte Message-ID: <20230127113451.ltx2l7u2a355qrde@orel> References: <20230127035306.1819561-1-guoren@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230127035306.1819561-1-guoren@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 26, 2023 at 10:53:06PM -0500, guoren@kernel.org wrote: > From: Guo Ren > > In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean > in __sync_icache_dcache()"), we found RISC-V has the same issue as the > previous arm64. The previous implementation didn't guarantee the correct > sequence of operations, which means flush_icache_all() hasn't been > called when the PG_dcache_clean was set. That would cause a risk of page > synchronization. > > Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable") > Signed-off-by: Guo Ren > Signed-off-by: Guo Ren > --- > Changelog: > V2: > - Optimize commit log > - Rebase on riscv for-next (20230127) > > V1: > https://lore.kernel.org/linux-riscv/20221023133205.3493564-2-guoren@kernel.org/ > --- > arch/riscv/mm/cacheflush.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > index 3cc07ed45aeb..fcd6145fbead 100644 > --- a/arch/riscv/mm/cacheflush.c > +++ b/arch/riscv/mm/cacheflush.c > @@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte) > if (PageHuge(page)) > page = compound_head(page); > > - if (!test_and_set_bit(PG_dcache_clean, &page->flags)) > + if (!test_bit(PG_dcache_clean, &page->flags)) { > flush_icache_all(); > + set_bit(PG_dcache_clean, &page->flags); > + } > } > #endif /* CONFIG_MMU */ > > -- > 2.36.1 > Reviewed-by: Andrew Jones Thanks, drew