Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B46C38142 for ; Fri, 27 Jan 2023 16:51:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233052AbjA0Qvs (ORCPT ); Fri, 27 Jan 2023 11:51:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232364AbjA0Qvk (ORCPT ); Fri, 27 Jan 2023 11:51:40 -0500 Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF2D77DBE6 for ; Fri, 27 Jan 2023 08:51:39 -0800 (PST) Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30R9k8LQ030633; Fri, 27 Jan 2023 10:51:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=G9V2GgFsHCD4LlZjSXpjsXaP7aw6r58g0ViRdqShLNs=; b=pAq8R4ogu88VG1tLwgWoH27+P9aCmKhssleshjJAYK/SBFd9xRgByHhUM/XFbK1gyado xzMihy/E0bZUuseesdpo3wWgTv+K8Tnbhi801cpY8uYsF6Q1SK3qKE4vXwYRSmZUMHUQ 0eGjKXVGl77nc065RLGPOPSbeSPDJsroeTMP50ACHvI+22HDWqMLl1waH2fgTC8FaWly F98ISowC1LV40mfe2aUVV/sgm5lsLvUCFlCRyCCBkWa0i8eGBBcjHRf8/Zkkd140FlIQ jNheJWJSyhYDorMx5YhJWRrsXh2b9vqV8Oua5vaP+/Pd4TSXabSwjyI95DDk7+qVHw0/ /g== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3n8dbsvrd1-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Jan 2023 10:51:31 -0600 Received: from ediex01.ad.cirrus.com (198.61.84.80) by ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.21; Fri, 27 Jan 2023 10:51:28 -0600 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.2.1118.21 via Frontend Transport; Fri, 27 Jan 2023 10:51:28 -0600 Received: from sbinding-cirrus-dsktp2.ad.cirrus.com (unknown [198.90.202.160]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 81BB1475; Fri, 27 Jan 2023 16:51:28 +0000 (UTC) From: Stefan Binding To: Vinod Koul , Bard Liao , Mark Brown , Pierre-Louis Bossart CC: , , , Richard Fitzgerald , Stefan Binding Subject: [PATCH v3 2/8] ASoC: cs42l42: Add SOFT_RESET_REBOOT register Date: Fri, 27 Jan 2023 16:51:05 +0000 Message-ID: <20230127165111.3010960-3-sbinding@opensource.cirrus.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230127165111.3010960-1-sbinding@opensource.cirrus.com> References: <20230127165111.3010960-1-sbinding@opensource.cirrus.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: f1gOs6M17WECR6i-8ovWH8yAllEhuxQj X-Proofpoint-GUID: f1gOs6M17WECR6i-8ovWH8yAllEhuxQj X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Richard Fitzgerald The SOFT_RESET_REBOOT register is needed to recover CS42L42 state after a Soundwire bus reset. This is required to be set whenever there is severe/hard bus reset. Signed-off-by: Richard Fitzgerald Signed-off-by: Stefan Binding --- include/sound/cs42l42.h | 5 +++++ sound/soc/codecs/cs42l42.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/include/sound/cs42l42.h b/include/sound/cs42l42.h index 1d1c24fdd0cae..3994e933db195 100644 --- a/include/sound/cs42l42.h +++ b/include/sound/cs42l42.h @@ -34,6 +34,7 @@ #define CS42L42_PAGE_24 0x2400 #define CS42L42_PAGE_25 0x2500 #define CS42L42_PAGE_26 0x2600 +#define CS42L42_PAGE_27 0x2700 #define CS42L42_PAGE_28 0x2800 #define CS42L42_PAGE_29 0x2900 #define CS42L42_PAGE_2A 0x2A00 @@ -720,6 +721,10 @@ #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09) +/* Page 0x27 DMA */ +#define CS42L42_SOFT_RESET_REBOOT (CS42L42_PAGE_27 + 0x01) +#define CS42L42_SFT_RST_REBOOT_MASK BIT(1) + /* Page 0x28 S/PDIF Registers */ #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01) #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02) diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c index 2fefbcf7bd130..82aa11d6937be 100644 --- a/sound/soc/codecs/cs42l42.c +++ b/sound/soc/codecs/cs42l42.c @@ -293,6 +293,7 @@ bool cs42l42_readable_register(struct device *dev, unsigned int reg) case CS42L42_SPDIF_SW_CTL1: case CS42L42_SRC_SDIN_FS: case CS42L42_SRC_SDOUT_FS: + case CS42L42_SOFT_RESET_REBOOT: case CS42L42_SPDIF_CTL1: case CS42L42_SPDIF_CTL2: case CS42L42_SPDIF_CTL3: @@ -358,6 +359,7 @@ bool cs42l42_volatile_register(struct device *dev, unsigned int reg) case CS42L42_LOAD_DET_DONE: case CS42L42_DET_STATUS1: case CS42L42_DET_STATUS2: + case CS42L42_SOFT_RESET_REBOOT: return true; default: return false; -- 2.34.1