Date:   Fri, 27 Jan 2023 22:53:05 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Atish Patra <atishp@rivosinc.com>
Cc:     linux-kernel@vger.kernel.org,
        Andrew Jones <ajones@ventanamicro.com>,
        Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@atishpatra.org>,
        Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
        kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
        linux-riscv@lists.infradead.org,
        Mark Rutland <mark.rutland@arm.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
        Will Deacon <will@kernel.org>
Subject: Re: [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related
 definitions
Message-ID: <Y9RV0cOMld20EFBI@spud>
References: <20230127182558.2416400-1-atishp@rivosinc.com>
 <20230127182558.2416400-4-atishp@rivosinc.com>
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Yo Atish,

On Fri, Jan 27, 2023 at 10:25:47AM -0800, Atish Patra wrote:
> This patch fixes/improve few minor things in SBI PMU extension
> definition.
>=20
> 1. Align all the firmware event names.

> @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t {
>  	SBI_PMU_FW_IPI_RECVD		=3D 7,
> -	SBI_PMU_FW_FENCE_I_RECVD	=3D 9,
> +	SBI_PMU_FW_FENCE_I_RCVD		=3D 9,
>  	SBI_PMU_FW_SFENCE_VMA_RCVD	=3D 11,

Alignment looks incomplete to me! Looks like you went from 2 RECVD and
1 RCVD to 2 RCVD and 1 RECVD! FWIW, the spec uses RECEIVED for all of
these:
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#1=
14-event-firmware-events-type-15

Thanks,
Conor.


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