Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 973F9C636CC for ; Sun, 29 Jan 2023 17:34:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235163AbjA2Rel (ORCPT ); Sun, 29 Jan 2023 12:34:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231707AbjA2Rei (ORCPT ); Sun, 29 Jan 2023 12:34:38 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09B641E2B8 for ; Sun, 29 Jan 2023 09:34:37 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id h16so9076450wrz.12 for ; Sun, 29 Jan 2023 09:34:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=5LhB+v37p+76x1E2O4Pvsff4S6wO2BA5elPpc0Squig=; b=BwJw9IqWegGmspNRnIEFiRkjyDbVKhKZr3x1pF0UtFZAvY9bV1tjRnTwaco1KESWnw wX5+qDQXPlq+8udFSMHVqmIPvr6v8k2sarIpSMXY4/qfw88hJ90g5/1iMY7Lv/t+PW3T z5ndUGgQHTXglZmhVtZ8F4rR4xzXQcEeYuny8xX4dFH0azcYd9aU+lfDBkE1ndTfNnY+ k1sxQD5FfpKqZXvuvA/A+IFHR86XzYXCsP/MDRpjnArzXUtl/4lInbAEmGWMAKUkPSjC 3gRiIL3l9eQk0y6uxGVCC1nzGT3F1uyUhleLVdvc9Gj8bueM3t//OllU8gvarEo4YEpt 4bJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=5LhB+v37p+76x1E2O4Pvsff4S6wO2BA5elPpc0Squig=; b=L9Ft7aL7X8mQlzIkJNIU4rp9eyC2A4A+rvLa88ZvdiY+Va+KlRK8ubWxSQdckd/VLE o9yC5lDgm4oRwgmPQbFUZHqdIjCCpadVyfYG9NfWaY37MIXiQriUZxkDkyT7W+Rf9T96 q5kr6+L4FIlf4aYfF+88woMT5pcv6PPu3LogBhaKJOfzYSytbN5R7vYNiEKomeSOL1QS Mm+aamZrEZxSC25hH0JIpNa044jhghAF5MqPIEq+7i/rT67hnFzazeNYbK4WgMAKR4dY oYkMnMQK4BYVht6yLY0n2ykcCewfgjJ0bnT6gNnSBtPF1zvTxaZkQthUqBDwhmaBM6g2 QfeQ== X-Gm-Message-State: AO0yUKVmP0DSvgJzrgyjKNbER9GmRIX1lGz5bxj/I6AnIpGxbLrQyqNS h+NJ+G3vmOEN2Aan6qY38symKg== X-Google-Smtp-Source: AK7set/ZqihGuUM8OBQtuR4yZAH6ZIXEV2MFHJy4fHsVKq1uTCbc0+HmZ8iyEmGyP3IWZMI7ncYHJQ== X-Received: by 2002:a05:6000:a17:b0:2bf:e766:90f4 with SMTP id co23-20020a0560000a1700b002bfe76690f4mr3119965wrb.68.1675013675608; Sun, 29 Jan 2023 09:34:35 -0800 (PST) Received: from linaro.org ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id d3-20020adfe2c3000000b002bc7fcf08ddsm9389546wrj.103.2023.01.29.09.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jan 2023 09:34:35 -0800 (PST) Date: Sun, 29 Jan 2023 19:34:33 +0200 From: Abel Vesa To: Oleksij Rempel Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Abel Vesa , Michael Turquette , Stephen Boyd , Richard Cochran , kernel@pengutronix.de, Fabio Estevam , NXP Linux Team , Russell King , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 02/19] clk: imx6q: add ethernet refclock mux support Message-ID: References: <20230117061453.3723649-1-o.rempel@pengutronix.de> <20230117061453.3723649-3-o.rempel@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230117061453.3723649-3-o.rempel@pengutronix.de> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23-01-17 07:14:36, Oleksij Rempel wrote: > Add ethernet refclock mux support and set it to internal clock by > default. This configuration will not affect existing boards since > machine code currently overwrites this default. > > The machine code will be fixed in a separate patch. > > Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa > --- > drivers/clk/imx/clk-imx6q.c | 13 +++++++++++++ > include/dt-bindings/clock/imx6qdl-clock.h | 4 +++- > 2 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c > index de36f58d551c..22b464ca22c8 100644 > --- a/drivers/clk/imx/clk-imx6q.c > +++ b/drivers/clk/imx/clk-imx6q.c > @@ -12,6 +12,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -115,6 +116,10 @@ static struct clk_div_table video_div_table[] = { > { /* sentinel */ } > }; > > +static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", }; > +static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD }; > +static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; > + > static unsigned int share_count_esai; > static unsigned int share_count_asrc; > static unsigned int share_count_ssi1; > @@ -908,6 +913,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) > hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; > > + hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0); > + > + hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr", > + IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels), > + enet_ref_sels_table, enet_ref_sels_table_mask); > + > imx_check_clk_hws(hws, IMX6QDL_CLK_END); > > of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); > @@ -974,6 +985,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); > } > > + clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk); > + > imx_register_uart_clocks(2); > } > CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); > diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h > index e20c43cc36f6..e5b2a1ba02bc 100644 > --- a/include/dt-bindings/clock/imx6qdl-clock.h > +++ b/include/dt-bindings/clock/imx6qdl-clock.h > @@ -273,6 +273,8 @@ > #define IMX6QDL_CLK_MMDC_P0_IPG 263 > #define IMX6QDL_CLK_DCIC1 264 > #define IMX6QDL_CLK_DCIC2 265 > -#define IMX6QDL_CLK_END 266 > +#define IMX6QDL_CLK_ENET_REF_SEL 266 > +#define IMX6QDL_CLK_ENET_REF_PAD 267 > +#define IMX6QDL_CLK_END 268 > > #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ > -- > 2.30.2 >