MIME-Version: 1.0
References: <20230127174014.251539-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592258905AC3979803C473D786CC9@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8s+cZpuUXWRa573a373n7YPsHrdLnUVXHjez6O101oneQ@mail.gmail.com>
 <OS0PR01MB5922943C1E1D9329691DB02F86CC9@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CAMuHMdWHE3wAYd7TSamN77Xy7CSxnEd8QHW8xm9ng4opsBEapg@mail.gmail.com>
 <CA+V-a8vBFSKbFJo1nEX7eN+S8eJazDDfCrzO7oFHsiF5yvpZ+g@mail.gmail.com> <874js8duh7.wl-maz@kernel.org>
In-Reply-To: <874js8duh7.wl-maz@kernel.org>
From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Mon, 30 Jan 2023 13:36:20 +0000
Message-ID: <CA+V-a8tvc1K=eHxGNGPvGjp4Ddz6jKu2b3w4+KE-SfJu0Qquvw@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
To:     Marc Zyngier <maz@kernel.org>
Cc:     Geert Uytterhoeven <geert@linux-m68k.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Hi Marc,

On Mon, Jan 30, 2023 at 1:26 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Mon, 30 Jan 2023 13:13:26 +0000,
> "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Geert,
> >
> > On Mon, Jan 30, 2023 at 10:05 AM Geert Uytterhoeven
> > <geert@linux-m68k.org> wrote:
> > >
> > > On Fri, Jan 27, 2023 at 10:48 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
> > > > > On Fri, Jan 27, 2023 at 6:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > > > Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU
> > > > > > > node
> > > > > > >
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > >
> > > > > > > Enable the performance monitor unit for the Cortex-A55 cores on the
> > > > > > > RZ/G2L
> > > > > > > (r9a07g044) SoC.
> > > > > > >
> > > > > > > Signed-off-by: Lad Prabhakar
> > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > ---
> > > > > > >  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++
> > > > > > >  1 file changed, 5 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > > > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > > > > index 80b2332798d9..ff9bdc03a3ed 100644
> > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > > > > @@ -161,6 +161,11 @@ opp-50000000 {
> > > > > > >               };
> > > > > > >       };
> > > > > > >
> > > > > > > +     pmu_a55 {
> > > > > > > +             compatible = "arm,cortex-a55-pmu";
> > > > > > > +             interrupts-extended = <&gic GIC_PPI 7
> > > > > > > + IRQ_TYPE_LEVEL_HIGH>;
> > > > > >
> > > > > > Just a question, Is it tested?
> > > > > Yes this was tested with perf test
> > > > >
> > > > > > timer node[1] defines irq type as LOW, here it is high.
> > > > > You are right looking at the RZG2L_InterruptMapping_rev01.xlsx this should
> > > > > be LOW. (I followed the SPI IRQS where all the LEVEL interrupts are HIGH)
> > > > >
> > > > > > Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as
> > > > > it has 2 cores??
> > > > > >
> > > > > No this is not required for example here [0] where it has 6 cores.
> > > >
> > > > I may be wrong, That is the only example[1], where the A55 PMU per cpu interrupts and number of a55 cores in the DT
> > > > are not matching.
> > > >
> > > > [1]
> > > > https://elixir.bootlin.com/linux/latest/B/ident/arm%2Ccortex-a55-pmu
> > >
> > > Indeed, this looks like an omission, propagated through
> > > arch/arm64/boot/dts/renesas/r8a779[afg]0.dtsi.
> > >
> > > And doesn't this apply to all PPI interrupts, i.e. shouldn't the GIC
> > > in arch/arm64/boot/dts/renesas/r9a07g0{43u,44u,54}.dtsi specify the
> > > mask in their interrupts properties, too?
> > >
> > I was under the impression that the GIC_CPU_MASK_SIMPLE(x) was only
> > needed if the driver handled per-cpu stuff.
> >
> > Marc, what should be the correct usage?
>
> I'm reading the DT correctly, this system has a GICv3, which is quite
> natural for an A55-based system. For this configuration, no mask is
> required.
>
> The CPU mask stuff only applies to pre-GICv3. With GICv3+, you simply
> cannot express such a mask, as there is no practical limit to the
> number of CPUs.
>
Thank you for the clarification.

Cheers,
Prabhakar