Date:   Mon, 30 Jan 2023 14:53:13 +0000
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Liao Chang <liaochang1@huawei.com>
CC:     <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
        <aou@eecs.berkeley.edu>, <heiko.stuebner@vrull.eu>,
        <ajones@ventanamicro.com>,
        <prabhakar.mahadev-lad.rj@bp.renesas.com>, <jszhang@kernel.org>,
        <vincent.chen@sifive.com>, <linux-riscv@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] riscv: Add header include guards to insn.h
Message-ID: <Y9fZ2ZxdMmXgO5aB@wendy>
References: <20230129094242.282620-1-liaochang1@huawei.com>
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Hey!

On Sun, Jan 29, 2023 at 05:42:42PM +0800, Liao Chang wrote:
> Add header include guards to insn.h to prevent repeating declaration of
> any identifiers in insn.h.

I'm curious, did you spot this "by hand" while doing other work, or do
you have a tool that found it for you?

> Fixes: edde5584c7ab ("riscv: Add SW single-step support for KDB")

Heh, I appreciate you going back to the file's original name to find the
correct fixes tag!
I figure that it's probably worth adding a fixes tag for the rename too,
so that the stable bots don't get confused? That would be:
Fixes: c9c1af3f186a ("RISC-V: rename parse_asm.h to insn.h")

Probably overkill when you have Drew's already for something so trivial,
but:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> Signed-off-by: Liao Chang <liaochang1@huawei.com>
> ---
>  arch/riscv/include/asm/insn.h | 4 ++++
>  1 file changed, 4 insertions(+)
>=20
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index 25ef9c0b19e7..22c7613bfda3 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -3,6 +3,9 @@
>   * Copyright (C) 2020 SiFive
>   */
> =20
> +#ifndef _ASM_RISCV_INSN_H
> +#define _ASM_RISCV_INSN_H
> +
>  #include <linux/bits.h>
> =20
>  #define RV_INSN_FUNCT3_MASK	GENMASK(14, 12)
> @@ -365,3 +368,4 @@ static inline void riscv_insn_insert_utype_itype_imm(=
u32 *utype_insn, u32 *itype
>  	*utype_insn |=3D (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1);
>  	*itype_insn |=3D ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF);
>  }
> +#endif /* _ASM_RISCV_INSN_H */
> --=20
> 2.25.1
>=20
>=20

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