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[2003:e4:1f20:1d00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id p14-20020a170906784e00b0084d34eec68esm7055612ejm.213.2023.01.30.07.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 07:54:57 -0800 (PST) Date: Mon, 30 Jan 2023 16:54:56 +0100 From: Thierry Reding To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: AngeloGioacchino Del Regno , krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com, john@phrozen.org, sean.wang@mediatek.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH v1 1/2] arm64: dts: mediatek: mt7622: Add missing pwm-cells to pwm node Message-ID: References: <20221128112028.58021-1-angelogioacchino.delregno@collabora.com> <20221128112028.58021-2-angelogioacchino.delregno@collabora.com> <20221202180932.5k3vymrwds5ssivq@pengutronix.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Tt+4zDA4srW5HLc6" Content-Disposition: inline In-Reply-To: <20221202180932.5k3vymrwds5ssivq@pengutronix.de> User-Agent: Mutt/2.2.9 (2022-11-12) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Tt+4zDA4srW5HLc6 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Dec 02, 2022 at 07:09:32PM +0100, Uwe Kleine-K=C3=B6nig wrote: > On Mon, Nov 28, 2022 at 12:20:27PM +0100, AngeloGioacchino Del Regno wrot= e: > > Specify #pwm-cells on pwm@11006000 to make it actually usable. > >=20 > > Fixes: ae457b7679c4 ("arm64: dts: mt7622: add SoC and peripheral relate= d device nodes") > > Signed-off-by: AngeloGioacchino Del Regno > > --- > > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + > > 1 file changed, 1 insertion(+) > >=20 > > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot= /dts/mediatek/mt7622.dtsi > > index 146e18b5b1f4..f321c6d0fd7c 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > > @@ -435,6 +435,7 @@ uart3: serial@11005000 { > > pwm: pwm@11006000 { > > compatible =3D "mediatek,mt7622-pwm"; > > reg =3D <0 0x11006000 0 0x1000>; > > + #pwm-cells =3D <2>; >=20 > 3 should be possible, too. The driver does only support one > polarity, so it's not really needed, but would be nice for consistency? >=20 > Thierry, what's your take here? There's little point in setting this to 3 if the driver doesn't support it. The core should catch misconfiguration, but that's more of a fail- safe and if we can just avoid this from the start by not allowing anyone to specify inversed polarity that seems like a good idea. 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