Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F2C4C636D3 for ; Mon, 30 Jan 2023 21:40:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229792AbjA3Vkd (ORCPT ); Mon, 30 Jan 2023 16:40:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231328AbjA3VkS (ORCPT ); Mon, 30 Jan 2023 16:40:18 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B59614E93 for ; Mon, 30 Jan 2023 13:40:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675114817; x=1706650817; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A80r7oChGS9LbqR+hFTuIEP18vZwaZTsItqNNyj9g5M=; b=ZtsGPKsHIq6wCx/m3kReHBMqDMp6+3HOE3M8RJ8Pc17FBbC/PWLjDFbW GEl50DD/VEK4FtP70OUki0VoZ6N6cCl2JW4sG19d5UjxnCxMT23IabSMU TXGkw4lQ7CZI6ske3zeKv0C+9fFj2mbF+EItV9T4SgBje9K5lcJpyWxQ1 lMUrnm5iUye5kLUm+EOnlQtNKAVs29z/hlbYyoj0u6ArSRgu8lde235FZ J9Uy0M+YznelwYX528+j4MfcdAleYTVtMI7XqUJkXSjI8koMrx6Qt0JuA gue8Eu/eL79uGUYi0fvtZRbDMeV62pZ6FFWTF5nOOf2JeR4xKfnTUZih1 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="328955565" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="328955565" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 13:40:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="696571879" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="696571879" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 13:40:13 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: Ashok Raj , Tony Luck , LKML , x86 , Ingo Molnar , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky , Martin Pohlack Subject: [Patch v3 Part2 8/9] x86/microcode/intel: Drop wbinvd() from microcode loading Date: Mon, 30 Jan 2023 13:39:54 -0800 Message-Id: <20230130213955.6046-9-ashok.raj@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230130213955.6046-1-ashok.raj@intel.com> References: <20230130213955.6046-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some older processors had a bad interaction when updating microcode if the caches were dirty causing machine checks. The wbinvd() was added to mitigate that before performing microcode updates. Now that Linux checks for the minimum version before performing an update, those microcode revisions can't be loaded. Early loading is also not required to use wbinvd() any longer, that was added as a safety net. Remove calls to wbinvd(). Signed-off-by: Ashok Raj Reviewed-by: Tony Luck Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky Cc: Martin Pohlack --- arch/x86/kernel/cpu/microcode/intel.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 98c92b9affa2..601c586be7b6 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -415,12 +415,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) old_rev = rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -632,12 +626,6 @@ static enum ucode_state apply_microcode_intel(int cpu) goto out; } - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); -- 2.37.2