Date:   Tue, 31 Jan 2023 21:46:25 +0800
From:   Clay Chang <clayc@hpe.com>
To:     Andrew Jeffery <andrew@aj.id.au>
CC:     <linux-kernel@vger.kernel.org>, <soc@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <verdun@hpe.com>,
        <nick.hawkins@hpe.com>, Arnd Bergmann <arnd@arndb.de>,
        "Rob Herring" <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Russell King <linux@armlinux.org.uk>,
        Olof Johansson <olof@lixom.net>
Subject: Re: [PATCH 0/5] ARM: Add GXP SROM Support
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Hi Andrew,

Thank you for taking time, and sorry for my late response.

On Fri, Jan 20, 2023 at 12:51:54PM +1030, Andrew Jeffery wrote:
> 
> 
> On Tue, 10 Jan 2023, at 14:55, clayc@hpe.com wrote:
> > From: Clay Chang <clayc@hpe.com>
> >
> > The GXP SROM control register can be used to configure LPC related
> > legacy I/O registers. Currently only the SROM RAM Offset Register
> > (vromoff) is exported.
> 
> What exact behaviour does vromoff influence? You mention I/O registers,
> but RAM offset feels like it may be related to MEM or FWH LPC cycles
> instead?
> 

Sorry for my previous inaccurate description about the vromoff register.
You are right, it is not related to I/O but memory LPC cycles. This
register defines the offset and size to BMC's memory for the system rom.
BMC uses it for system rom related operations. One way to access this is
through the memory LPC cycles.

> I'm trying to understand whether we can find some common ground with
> controlling e.g. Aspeed's BMCs LPC peripherals based on Arnd's query[1],
> but the description is a bit too vague right now for me to be able to do
> that.
> 
> [1] https://lore.kernel.org/all/66ef9643-b47e-428d-892d-7c1cbd358a5d@app.fastmail.com/
> 
> Andrew

Thanks,
Clay