Message-ID: <b1ea8d3b-d5f4-0aac-d7b4-45fef9afe778@intel.com>
Date:   Wed, 1 Feb 2023 10:20:33 -0800
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Subject: Re: [PATCH 3/7] x86/cpu: Disable kernel LASS when patching kernel
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To:     Sohil Mehta <sohil.mehta@intel.com>,
        "Chen, Yian" <yian.chen@intel.com>, linux-kernel@vger.kernel.org,
        x86@kernel.org, Andy Lutomirski <luto@kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Ravi Shankar <ravi.v.shankar@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Paul Lai <paul.c.lai@intel.com>
References: <20230110055204.3227669-1-yian.chen@intel.com>
 <20230110055204.3227669-4-yian.chen@intel.com>
 <693d8332-3b86-3dcf-fc87-5c3a08a752db@intel.com>
 <ad2da884-c8c8-bc57-e21f-452a08cb10cc@intel.com>
 <b9e73d06-bd95-7c54-3ff1-f9e43c9967a4@intel.com>
 <9e0a8b20-cb76-b06d-67fb-f8942df5a2f7@intel.com>
 <f8352c29-6b9f-2711-ddf4-223a6806f42f@intel.com>
 <ed41ccf1-8f2d-6d4a-7692-7a3465aca73a@intel.com>
From:   Dave Hansen <dave.hansen@intel.com>
In-Reply-To: <ed41ccf1-8f2d-6d4a-7692-7a3465aca73a@intel.com>
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On 1/31/23 18:25, Sohil Mehta wrote:
>> 	/*
>> 	 * Set cr4 to a known state:
>> 	 *  - physical address extension enabled
>> 	 *  - 5-level paging, if it was enabled before
>> 	 */
>> 	movl	$X86_CR4_PAE, %eax
>> 	testq	$X86_CR4_LA57, %r13
>> 	jz	1f
>> 	orl	$X86_CR4_LA57, %eax
>> 1:
>> 	movq	%rax, %cr4
>>
>> 	jmp 1f
>> 1:
> Dave, does this address your concern or were you looking for something
> else? Is there some path other than kexec that should also be audited
> for this scenario?

Yep, that addresses it.  I don't know of any other path that would
matter.  Couldn't hurt to poke around and look for other CR4
manipulation that might need to be LASS-aware, though.