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From:   Robert Marko <robimarko@gmail.com>
Date:   Thu, 2 Feb 2023 10:16:14 +0100
Message-ID: <CAOX2RU5Y642gWMSaK6fJ2tz=9N2AO-1fFhL5=wfLeTWWkVjz7Q@mail.gmail.com>
Subject: Re: [PATCH v2 8/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node
To:     Arnd Bergmann <arnd@arndb.de>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>, bhelgaas@google.com,
        lpieralisi@kernel.org, Rob Herring <robh@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
        krzysztof.kozlowski+dt@linaro.org,
        Manivannan Sadhasivam <mani@kernel.org>, svarbanov@mm-sol.com,
        shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, Abel Vesa <abelvesa@kernel.org>
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On Mon, 30 Jan 2023 at 18:11, Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Fri, Jan 13, 2023, at 17:44, Robert Marko wrote:
> > IPQ8074 comes in 2 silicon versions:
> > * v1 with 2x Gen2 PCIe ports and QMP PHY-s
> > * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
> >
> > v2 is the final and production version that is actually supported by the
> > kernel, however it looks like PCIe related nodes were added for the v1 SoC.
> >
> > Finish the PCIe fixup by using the correct compatible, adding missing ATU
> > register space, declaring max-link-speed, use correct ranges, add missing
> > clocks and resets.
> >
> > Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
>
> I was reading through the pull request today and saw this patch
> along with the Gen2 one:
>
>
> > @@ -871,9 +873,9 @@ pcie0: pci@20000000 {
> >                       phy-names = "pciephy";
> >
> >                       ranges = <0x81000000 0 0x20200000 0x20200000
> > -                               0 0x100000   /* downstream I/O */
> > +                               0 0x10000>, /* downstream I/O */
>
> Fixing the length here seems fine, but the bus-side address
> still looks wrong: 0x20200000 is way outside of the usual
> port ranges from 0 to 0x10000 on the local bus.
>
> > -                               0x82000000 0 0x20300000 0x20300000
> > -                               0 0xd00000>; /* non-prefetchable memory */
> > +                              <0x82000000 0 0x20220000 0x20220000
> > +                               0 0xfde0000>; /* non-prefetchable memory */
>
> I see the total size of the memory space is under 256MB. Are you
> sure that there is no 64-bit BAR in addition to this?
>
> I also see commit 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add
> PCIe PHYs and controllers nodes") introduce the same broken
> I/O port range (oversized 1MB space wiht an identity map) for a
> new SoC. This should probably be fixed as well, along with
> reviewing the other ones.
>
> Has the I/O space mapping on any of these actually been tested,
> or just copied from one SoC to another? Very few devices actually
> use I/O space, so it wouldn't be surprising if it never worked
> in the first place.

Hi Arnd,
As pointed out in the commit description, the ranges property was copied
from the QCA-s downstream 5.4 kernel [1] as I dont have any documentation
on the SoC.

I have runtime tested this on Xiaomi AX3600 which has a QCA9889 card on the
Gen3 PCIe port, and on Xiaomi AX9000 which has QCA9889 on Gen2 port
and QCN9074 on the Gen3 port and they are working fine.

[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.3.r2/arch/arm64/boot/dts/qcom/ipq8074.dtsi#L834

Regards,
Robert
>
>        Arnd