Message-ID: <4b616f6c-2df3-e2c5-162e-356111d18bb9@foss.st.com>
Date:   Thu, 2 Feb 2023 13:26:41 +0100
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Subject: Re: [PATCH] ARM: dts: stm32: Update part number NVMEM description on
 stm32mp131
To:     Patrick Delaunay <patrick.delaunay@foss.st.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Arnd Bergmann <arnd@arndb.de>
CC:     <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-stm32@st-md-mailman.stormreply.com>
References: <20230118134948.1.Ica923e4a2407c976dcf3d65c266c27c883734dd8@changeid>
Content-Language: en-US
From:   Alexandre TORGUE <alexandre.torgue@foss.st.com>
In-Reply-To: <20230118134948.1.Ica923e4a2407c976dcf3d65c266c27c883734dd8@changeid>
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On 1/18/23 13:49, Patrick Delaunay wrote:
> The STM32MP13x Device Part Number (also named RPN in reference manual)
> only uses the first 12 bits in OTP4, all the other bit are reserved and
> they can be different of zero; they must be masked in NVMEM result, so
> the number of bits must be defined in the nvmem cell description.
> 
> Fixes: 1da8779c0029 ("ARM: dts: stm32: add STM32MP13 SoCs support")
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
> ---
> 
>   arch/arm/boot/dts/stm32mp131.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
> index f50051e81ee3..2f186a0ae92e 100644
> --- a/arch/arm/boot/dts/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
> @@ -1233,6 +1233,7 @@ bsec: efuse@5c005000 {
>   
>   			part_number_otp: part_number_otp@4 {
>   				reg = <0x4 0x2>;
> +				bits = <0 12>;
>   			};
>   			ts_cal1: calib@5c {
>   				reg = <0x5c 0x2>;
Applied on stm32-next.

Thanks.
Alex