Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92920C61DA4 for ; Thu, 2 Feb 2023 15:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232178AbjBBPkD (ORCPT ); Thu, 2 Feb 2023 10:40:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232940AbjBBPjo (ORCPT ); Thu, 2 Feb 2023 10:39:44 -0500 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B46F323C7D; Thu, 2 Feb 2023 07:39:22 -0800 (PST) Received: from toolbox.int.toradex.com ([213.55.225.17]) by mrelay.perfora.net (mreueus003 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MEovc-1pPHKo0GjK-00FxTh; Thu, 02 Feb 2023 16:33:00 +0100 From: Marcel Ziswiler To: devicetree@vger.kernel.org Cc: Liu Ying , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-imx@nxp.com, Joakim Zhang , Marcel Ziswiler , Alexander Stein , Fabio Estevam , Frank Li , Krzysztof Kozlowski , Max Krummenacher , Peng Fan , Pengutronix Kernel Team , Philippe Schenker , Rob Herring , Sascha Hauer , Shawn Guo Subject: [PATCH v6 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Thu, 2 Feb 2023 16:32:15 +0100 Message-Id: <20230202153221.197308-6-marcel@ziswiler.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230202153221.197308-1-marcel@ziswiler.com> References: <20230202153221.197308-1-marcel@ziswiler.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:hVpPGSSdqpj7zPNz82c0jzvaidawDWXxruHfRDfxUAbPCFzD5yl dTUapQCqAOifspwfwoNrG9UhQlWgzMNN+1rUADisFDW/8Jd9wNKmGvhzJR2HtKvn+YLIGD4 9nyN5ItlE2iv+PAweoApThnnpZzJb8Er/98SazV67ruIL2RvNwxFlWJevpKV1WXwD4cR2d8 FK/zzW3srVCAj/MrdrIYA== UI-OutboundReport: notjunk:1;M01:P0:W44o0CjZzCk=;nHA9RDqEMsxlHnZ6Wi4VXC0Iczl SMdvdiVpFSLs/yCbW+nTlIb0eHX+R/8oVN5cNQT+prsMnzOfbJBAruROjIkaCNxWfHSIkg4UN WOM5mu0nFTtergoM902Z6jzjSZnqTGPzlhiSRl1uebnylG45+b9GiBtYyikrpAWns92LYXZBP bDFGoehz+ymOXSH6SQl5x5PKSc4wsqKcThNMLEqTFbqgfivPLAmRvT9VKvNX497tqXn1i4DJF I+PsCzir+55v9S0PA1onomYNsLPxh+B2rqvaZD0oZLitN+RJBpFVQFEbSKmN0Fr8YfL14NcXL kflMZ2VhFgou0qRtQVOclBqwTBUxW1rn8khQNaDV06YKaxjos7w7z8lXOX/lq/tdFFTe5jfag fsnzax0Ql6ZsWGQCz4Il4cxGkcyima4mmH8he7azDW4KtEoLFAwPcpO/pvrBftRuRJ3K6RnOz 060eKw4+A811W2p+xzJMCrY9eRBcKGWff+wec+MPmlAhcp44TNpzzBA8oIaA89potRwX98LEE WjuIlXf8i45NTHMnEu0WJHKq1KVfJZJ7izpSJCI94ICWLPj8ulkmNrDBgT/28zTQrCyzhIKlc gghn5yxF/nhPMERXBy/dojb/xmiTbEbPXrZm57VQdvSJgUbg63dnSSa6lm4kItTevOeF+ZiUB R2NW0YZAvIpQE0OCpkog3N/iE4C1Rpxe+G0PvcfvCg== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joakim Zhang Add FlexCAN decive in adma subsystem. Signed-off-by: Joakim Zhang Signed-off-by: Marcel Ziswiler Tested-by: Alexander Stein # TQMa8XQP --- Changes in v6: - Add Alexander's tested-by. Thanks! Changes in v4: - New patch combining the following downstream patches: commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN fsl,clk-source and fsl,scu-index property") .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6ccf926b77a5..2dce8f2ee3ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -298,6 +298,65 @@ adc1: adc@5a890000 { status = "disabled"; }; + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { "adc1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_ADC_1>; }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = , , ; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; }; -- 2.36.1