Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC00BC05027 for ; Mon, 6 Feb 2023 09:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229478AbjBFJLb (ORCPT ); Mon, 6 Feb 2023 04:11:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230001AbjBFJLY (ORCPT ); Mon, 6 Feb 2023 04:11:24 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 102F646BC; Mon, 6 Feb 2023 01:11:20 -0800 (PST) X-UUID: 33306b98a5fe11eda06fc9ecc4dadd91-20230206 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zKrcHq1RH7vXZiYx8/L8KIQi6d51DIHCx1EYCn36Oq8=; b=CyfIjN5gnieERMV90ZtupKpnHrcsf4w1zWX/sgIFOi5toFTvFq96pAP9SLbyXUdHGBrDyOFIUFTdsi+uKUImz5No3BeKr1jIt5If9pm56jVhIgcULUB3dqdpKnebeo5WzSkDxOMeGb/MXJHXFUqTH5Ya6h+3iGSe9FoYvdH2W/8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:cf9574c8-d092-4b39-a37b-2983fa29aabd,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:885ddb2,CLOUDID:0f2599f7-ff42-4fb0-b929-626456a83c14,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 33306b98a5fe11eda06fc9ecc4dadd91-20230206 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1495617755; Mon, 06 Feb 2023 17:11:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 6 Feb 2023 17:11:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 6 Feb 2023 17:11:10 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Michael Turquette , Stephen Boyd CC: , , , , , , Moudy Ho Subject: [PATCH v7 3/6] arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS Date: Mon, 6 Feb 2023 17:11:06 +0800 Message-ID: <20230206091109.1324-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230206091109.1324-1-moudy.ho@mediatek.com> References: <20230206091109.1324-1-moudy.ho@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In MT8195, the MMSYS has two Video Processor Pipepline Subsystems named VPPSYS0 and VPPSYS1, each with specific MUTEX to control Start of Frame(SOF) and End of Frame (EOF) signals. Before working with them, the addresses, interrupts, clocks and power domains need to be set up in dts. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 526136703142..8fc527570791 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1801,6 +1801,15 @@ #clock-cells = <1>; }; + mutex@1400f000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { compatible = "mediatek,mt8195-smi-sub-common"; reg = <0 0x14010000 0 0x1000>; @@ -1906,6 +1915,15 @@ #clock-cells = <1>; }; + mutex@14f01000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x14f01000 0 0x1000>; + interrupts = ; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x14f02000 0 0x1000>; -- 2.18.0