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From:   Terry Bowman <terry.bowman@amd.com>
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        <bp@suse.de>, <feng.tang@intel.com>, <x86@kernel.org>
Subject: [PATCH 1/3] tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007
Date:   Mon, 6 Feb 2023 08:18:30 -0600
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Leaf Fn00000007 contains avx512bw at bit26 and avx512vl at bit28. This
is incorrect per the SDM. Correct avx512bw to be bit30 and avx512lvl to be
bit31.[1]

[1] Intel 64 and IA-32 Architectures Software Developer's Manual
    Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4, December
    2022, pg 3-220,Vol2A

Fixes: c6b2f240bf8d ("tools/x86: Add a kcpuid tool to show raw CPU features")
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Cc: feng.tang@intel.com <feng.tang@intel.com>
Cc: x86@kernel.org
---
 tools/arch/x86/kcpuid/cpuid.csv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index 4f1c4b0c29e9..9914bdf4fc9e 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -184,8 +184,8 @@
 	 7,    0,  EBX,     27, avx512er, AVX512 Exponent Reciproca instr
 	 7,    0,  EBX,     28, avx512cd, AVX512 Conflict Detection instr
 	 7,    0,  EBX,     29, sha, Intel Secure Hash Algorithm Extensions instr
-	 7,    0,  EBX,     26, avx512bw, AVX512 Byte & Word instr
-	 7,    0,  EBX,     28, avx512vl, AVX512 Vector Length Extentions (VL)
+	 7,    0,  EBX,     30, avx512bw, AVX512 Byte & Word instr
+	 7,    0,  EBX,     31, avx512vl, AVX512 Vector Length Extentions (VL)
 	 7,    0,  ECX,      0, prefetchwt1, X
 	 7,    0,  ECX,      1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
 	 7,    0,  ECX,      2, umip, User-mode Instruction Prevention
-- 
2.34.1