Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED7F7C63797 for ; Mon, 6 Feb 2023 16:30:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229999AbjBFQav (ORCPT ); Mon, 6 Feb 2023 11:30:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229523AbjBFQat (ORCPT ); Mon, 6 Feb 2023 11:30:49 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6848BBAE; Mon, 6 Feb 2023 08:30:46 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 2305724E01A; Tue, 7 Feb 2023 00:30:44 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 00:30:44 +0800 Received: from [172.16.16.234] (113.72.145.145) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 00:30:43 +0800 Message-ID: Date: Tue, 7 Feb 2023 00:30:41 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 1/4] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl Content-Language: en-US To: Rob Herring CC: , , , Conor Dooley , Palmer Dabbelt , Krzysztof Kozlowski , Linus Walleij , Andreas Schwab , "Emil Renner Berthing" , Jianlong Huang , References: <20230203141801.59083-1-hal.feng@starfivetech.com> <20230203141801.59083-2-hal.feng@starfivetech.com> <20230206161016.GA156592-robh@kernel.org> From: Hal Feng In-Reply-To: <20230206161016.GA156592-robh@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.145.145] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 6 Feb 2023 10:10:16 -0600, Rob Herring wrote: > On Fri, Feb 03, 2023 at 10:17:58PM +0800, Hal Feng wrote: >> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml >> new file mode 100644 >> index 000000000000..22554e68ec91 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml >> @@ -0,0 +1,141 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive JH7110 SYS Pin Controller >> + >> +description: | >> + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. >> + >> + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 >> + can be multiplexed and have configurable bias, drive strength, >> + schmitt trigger etc. >> + Some peripherals have their I/O go through the 64 "GPIOs". This also >> + includes a number of other UARTs, I2Cs, SPIs, PWMs etc. >> + All these peripherals are connected to all 64 GPIOs such that >> + any GPIO can be set up to be controlled by any of the peripherals. >> + >> +maintainers: >> + - Jianlong Huang >> + >> +properties: >> + compatible: >> + const: starfive,jh7110-sys-pinctrl >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + '#interrupt-cells': >> + const: 2 >> + >> + gpio-controller: true >> + >> + '#gpio-cells': >> + const: 2 >> + >> +patternProperties: >> + '-[0-9]+$': >> + type: object >> + additionalProperties: false >> + patternProperties: >> + '-pins$': >> + type: object >> + description: | >> + A pinctrl node should contain at least one subnode representing the >> + pinctrl groups available on the machine. Each subnode will list the >> + pins it needs, and how they should be configured, with regard to >> + muxer configuration, bias, input enable/disable, input schmitt >> + trigger enable/disable, slew-rate and drive strength. >> + $ref: /schemas/pinctrl/pincfg-node.yaml > > On 2nd look, this should be: > > allOf: > - $ref: /schemas/pinctrl/pincfg-node.yaml > - $ref: /schemas/pinctrl/pinmux-node.yaml Will fix accordingly. Thanks. > >> + additionalProperties: false >> + >> + properties: >> + pinmux: >> + description: | >> + The list of GPIOs and their mux settings that properties in the >> + node apply to. This should be set using the GPIOMUX or PINMUX >> + macros. >> + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux > > And drop this. > > Same in other patch. With that, Reviewed-by stands. Will fix it. Thank you for your review. Best regards, Hal