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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT112.mail.protection.outlook.com (10.13.174.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6064.35 via Frontend Transport; Mon, 6 Feb 2023 17:58:49 +0000 Received: from [10.236.30.70] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 6 Feb 2023 11:58:47 -0600 Message-ID: <7abdd9d4-4ce0-458d-93f4-bff575f04345@amd.com> Date: Mon, 6 Feb 2023 11:58:47 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 To: David Woodhouse , Usama Arif , , CC: , , , , , , , , , , , , , , , , , , , Mario Limonciello References: <20230202215625.3248306-1-usama.arif@bytedance.com> <20230202215625.3248306-8-usama.arif@bytedance.com> Content-Language: en-US From: Kim Phillips Subject: Re: [PATCH v6 07/11] x86/smpboot: Disable parallel boot for AMD CPUs In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2023 17:58:49.6005 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f83e067-5764-4648-6ff7-08db086bcd0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT112.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6098 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/4/23 9:40 AM, David Woodhouse wrote: > On Fri, 2023-02-03 at 13:48 -0600, Kim Phillips wrote: >> If I: >> >>   - take dwmw2's parallel-6.2-rc6 branch (commit 459d1c46dbd1) >>   - remove the set_cpu_bug(c, X86_BUG_NO_PARALLEL_BRINGUP) line from amd.c >> >> Then: >> >>   - a Ryzen 3000 (Picasso A1/Zen+) notebook I have access to fails to boot. >>   - Zen 2,3,4-based servers boot fine >>   - a Zen1-based server doesn't boot. > > I've changed it to use CPUID 0xb only if we're actually in x2apic mode, > which Boris tells me won't be the case on Zen1 because that doesn't > support X2APIC. > > When we're not in x2apic mode, we can use CPUID 0x1 because the 8 bits > of APIC ID we find there are perfectly sufficient. > > New tree in the same place as before, commit ce7e2d1e046a for the > parallel-6.2-rc6-part1 tag and 17bbd12ee03 for parallel-6.2-rc6. Thanks, Zen 1 through 4 based servers all boot both those two tree commits successfully. I'll try that Ryzen again later. Kim